Spansion Llc.

Advanced Micro Devices Corporation

Lam Research Corporation

Cypress Semiconductor Corporation

Phillip Lawrence Jones

Angela Tai Hui

Scott Allan Bell

Calvin T Gabriel

Mark S Chang

Fei Wang

Shenqing Fang

Kuo-Tung Chang

Simon S Chan

Ning Cheng

Alexander H Nickel

Lei Xue

Allison Holbrook

Huaqiang Wu

Roger Patrick

Harpreet Kaur Sachar

Minh-Van Ngo

Jihwan Choi

Hiro Kinoshita

Zubin Patel

Shankar Sinha

Seyed Jafar Jafarian-Tehrani

Jean Yee-Mei Yang

Ching-Hwa Chen

Weidong Qian

John C Foster

David R-Chen Liu

Yun-Yen Jack Yang

Wen-Ben Chou

Vidyut Gopal

Ken Edward Tokunaga

Boris V Atlas

Kambiz Fallahpour

In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Dielectric extension to mitigate short channel effects

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line.

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.

Enhanced etching of a high dielectric constant layer

A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.

Isolation region bird's beak suppression

A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

Etch process for CD reduction of arc material

A method includes forming a group of first structures on a semiconductor device and forming spacers adjacent side surfaces of each of the first structures to form a group of second structures. The method further includes using the group of second structures to form at least one sub-lithographic opening in a material layer located below the group of second structures.

Polymer spacers for creating sub-lithographic spaces

An apparatus and method in a plasma processing chamber for reducing charging of a wafer is described. A plasma generating element is configured to cause a plasma including ions and free radicals to be formed in a plasma generating region. A plasma diffusion region is configured so that plasma generated in the plasma generating region can diffuse through the plasma diffusion region. A conductive grid is positioned within the plasma diffusion region between the wafer and the plasma generating region. The conductive grid includes a mesh which is configured to trap a portion of the ions so that a portion of the ions are prevented from diffusing through the diffusion region to reach the wafer.

Methods and apparatus for reducing charging during plasma processing

A charge monitoring apparatus measures an electrical charge deposited on a multiple-layered workpiece, such as a semiconductor wafer, in a plasma processing system. The apparatus includes a charge collection electrode (CCE), a non-conducting patterned layer and a voltage or current sensor. The patterned layer is provided on the CCE and includes a plurality of openings that extend through the patterned layer to the conducting surface of the CCE. The openings create a topology having an adequate aspect ratio to cause electron shading to occur during plasma processing of the workpiece. The voltage or current sensor includes an EEPROM transistor that stores information regarding the amount of electrical charge that accumulates on the CCE during plasma processing.

Methods and apparatus for detecting pattern dependent charging on a

An electrostatic chuck system having an electrostatic chuck for securely holding a wafer on a surface of the electrostatic chuck. The electrostatic chuck system comprises a wafer bias sensor coupled to a first portion of the electrostatic chuck for sensing an alternating current signal at the first portion. The wafer bias sensor outputs, responsive to the alternating current signal, a direct current voltage level representative of a direct current bias level of the wafer. The electrostatic chuck system further comprises a variable electrostatic chuck power supply coupled to the wafer bias sensor. The variable electrostatic chuck power supply provides a first potential level to the first portion of the electrostatic chuck. The first potential level is modified, responsive to the direct current voltage level, to substantially maintain a first predefined potential difference between the first portion of the electrostatic chuck and a first region of the wafer overlaying the first portion irrespective of a magnitude of the direct current bias level of the wafer.

Dynamic feedback electrostatic wafer chuck

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Fremont, CA, United States of America

Phillip Lawrence Jones