International Business Machines Corporation

Phillip G Williams

Guy L Guthrie

William John Starke

Derek E Williams

Hugh Shen

Geraint M North

Jeffrey A Stuecheli

Naresh Nayar

Hien Le

Brian William Thompto

Sanjeev Ghai

Dung Q Nguyen

Steven R Carlough

Sheldon Bernard Levenstein

Timothy Carl Bronson

Jeff A Stuecheli

Harmony Lynn Helterhoff

Michael Steven Siegel

Sundeep Chadha

Christian Zoellin

Kurt Alan Feiste

Alvan Wing Ng

John M Sheplock

James Stephen Fields, Jr

Bernard Charles Drerup

Brian David Barrick

Kevin Franklin Reick

Albert James Van Norstrand, Jr

Glenn David Gilda

Thomas L Jeremiah

Niels Fricke

Mehul N Patel

Stefan P Jackowski

Paul M Kennedy

Hung Qui Le

Bartholomew Blaner

Benjiman L Goodman

Jose Eduardo Moreira

David S Levitan

Stamatis Vassiliadis

Leo James Clark

Bryan J Lloyd

David Allen Hrusecky

Robert Alan Cargnoni

Bruce Leroy Beukema

Ronald Edward Fuhs

Michael Joseph Genden

Anthony J Bybell

James Wilson Bishop

David W Cummings

Nicholas R Orzol

Robert Benjamin Gass

Jessica Hui-Chun Tseng

Marcy Evelyn Byers

William Garrett Verdoorn, Jr

Tharunachalam Pindicura

Kent Li

Christian Gerhard Zoellin

Guy Lynn Gutherie

Dorothea A Williams

Nir Segev

A computer system, processor, programming instructions and/or method for balancing the workload of processing pipelines that includes an execution slice, the execution slice comprising at least two processing pipelines having one or more execution units for processing instructions, wherein at least a first processing pipeline and a second processing pipeline are capable of executing a first instruction type; and an instruction decode unit for decoding instructions to determine which of the first processing pipeline or the second processing pipeline to execute the first instruction type. The processor configured to calculate at least one of a workload group consisting of: the first processing pipeline workload, the second processing pipeline workload, and combinations thereof; and select the first processing pipeline or the second processing pipeline to execute the first instruction type based upon at least one of the workload group.

Routing instructions in a microprocessor

Technology for fusing certain load instructions and compare-immediate instructions in a computer processor having a load-store architecture with respect to transferring data between memory and registers of the computer processor. In some embodiments the load and compare-immediate instructions are consecutive. In some embodiments, the instructions are only merged if: (i) the respective RA and RT fields of the two instructions match; (ii) the immediate field of the compare-immediate instruction has a certain value, or falls within a range of certain values; and/or (iii) the instructions are received in a consecutive manner.

Microprocessor that fuses load and compare instructions

Load store addressing can include a processor, which fuses two consecutive instruction determined to be prefix instructions and treats the two instructions as a single fused instruction. The prefix instruction of the fused instruction is auto-finished at dispatch time in an issue unit of the processor. A suffix instruction of the fused instruction and its fields and the prefix instruction's fields are issued from an issue queue of the issue unit, wherein an opcode of the suffix instruction is issued to a load store unit of the processor, and fields of the fused instruction are issued to the execution unit of the processor. The execution unit forms operands of the suffix instruction, at least one operand formed based on a current instruction address of the single fused instruction. The load store unit executes the suffix instruction using the operands formed by the execution unit.

Program counter (PC)-relative load and store addressing for fused instructions

Technology for fusing an add-immediate instruction with a load-immediate instruction (or store-immediate instruction) in a microprocessor. This can result in quicker address generation while performing a load and store operation.

Fusion to enhance early address generation of load instructions in a microprocessor

Statistical data is used to enable or disable snooping on a bus of a processor. A command is received via a first bus or a second bus communicably coupling processor cores and caches of chiplets on the processor. Cache logic on a chiplet determines whether or not a local cache on the chiplet can satisfy a request for data specified in the command. In response to determining that the local cache can satisfy the request for data, the cache logic updates statistical data maintained on the chiplet. The statistical data indicates a probability that the local cache can satisfy a future request for data. Based at least in part on the statistical data, the cache logic determines whether to enable or disable snooping on the second bus by the local cache.

Adaptively enabling and disabling snooping bus commands

Processor instruction scheduling by: providing a set of program instructions, selecting instructions for reordering from the set of program instructions, reordering the instructions according to instruction properties, assigning sequential instruction tags to the instructions, tagging the instructions for completion as a group in a completion table; and executing the instructions.

Program instruction scheduling

A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

A set-associative cache memory includes a plurality of ways and a plurality of congruence classes. Each of the plurality of congruence classes includes a plurality of members each belonging to a respective one of the plurality of ways. In the cache memory, a data structure records a history of an immediately previous N ways from which cache lines have been evicted. In response to receipt of a memory access request specifying a target address, a selected congruence class among a plurality of congruence classes is selected based on the target address. At least one member of the selected congruence class is removed as a candidate for selection for victimization based on the history recorded in the data structure, and a member from among the remaining members of the selected congruence class is selected. The cache memory then evicts the victim cache line cached in the selected member of the selected congruence class.

Victim cache line selection

Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Operation of a multi-slice processor implementing datapath steering, where the multi-slice processor includes a plurality of execution slices. Operation of such a multi-slice processor includes: identifying, from a set of instructions, a second instruction that is dependent upon a first instruction in the set of instructions; and responsive to the second instruction being dependent upon the first instruction in the set of instructions, issuing each of the instructions in the set of instructions to a particular set of execution slices configured with bypass logic between execution slices that reduces execution latencies between dependent instructions.

Operation of a multi-slice processor implementing datapath steering

Methods and apparatus for thread migration using a microcode engine of a multi-slice processor including issuing a thread migration instruction to the microcode engine of a decode unit, the thread migration instruction comprising an indication that the thread migration instruction is to be processed by the microcode engine; decoding, by the microcode engine, the thread migration instruction into a plurality of internal operations each targeting a different register entry; transmitting the plurality of internal operations to a dispatcher of the multi-slice processor; and manipulating, by the multi-slice processor, a plurality of register entries according to the plurality of internal operations.

Thread migration using a microcode engine of a multi-slice processor

Method for flagging data modification during a virtual machine backup

System for flagging data modification during a virtual machine backup

Growing community of inventors

Leander, TX, United States of America

Phillip G Williams