Intel Corporation

Phillip G Lee

Milind A Karnik

Blair D Milburn

Gurbir Singh

Eileen Riggs

Randy L Steck

Truong Nguyen

Robert M Riches, Jr

A method and apparatus for providing an interface from a processor to a bus. The interface is capable of operating at a speed selected from a plurality of speeds. An execution unit is coupled to a register file. The register file comprises a plurality of registers. Each of the registers of the register file is for storing data. The execution unit is for executing instructions. An instruction cache is coupled to the execution unit. The instruction cache and ROM is for storing instructions that can be used by the execution unit. A reset means is also coupled to the execution unit. Furthermore, a bus speed indication means is coupled to the execution unit and to the register files. The bus speed indication means is for receiving a bus speed indication signal. The bus speed indication signal is for indicating the selected operating speed for the bus interface. The reset signal is provided to the reset means and the bus speed indication signal is provided to the bus speed indication means. Upon receipt of the reset signal, the reset means causes a predetermined string of instructions to be retrieved from the instruction cache and to be executed by the execution unit. A first instruction of the predetermined string of instructions causes a value to be stored in a predetermined register of the register file. The value stored in the predetermined register of the register file is set according to the bus speed indication signal that was provided. A second instruction of the predetermined string of instructions, executed after the first instruction, provides the value stored in the predetermined register of the register file to the bus interface and thereby causes the bus interface to enter a mode wherein the bus interface operates at the selected speed specified by the bus speed indication signal.

Selection from a plurality of bus operating speeds for a processor bus

A cache control method and mechanism for an external cache memory having multiple cache lines using interagent communications to cause invalidating the external cache memory, flushing the external cache memory and/or changing the coherency state of lines in the external cache memory.

Method and apparatus for controlling an external cache memory wherein

A late cancel method and apparatus for a high performance microprocessor system is disclosed. The invention is advantageously utilized in a microprocessor system comprising a processor, an external cache memory and a main memory. The processor incorporates logic to determine whether an access directed to the external cache memory has resulted in a cache hit or miss. In operation, the processor requests a desired instruction from the external cache memory which provides a cache word and cache tag to the processor before a validity determination has been made. The processor determines whether the instruction is valid, while concurrently, the processor begins to pre-decode and decode the cache word as an instruction. If the processor determines that a cache hit has occurred, the cache word proceeds normally through decoding to execution by the processor. Alternatively, if the processor determines that a cache miss has occurred, the cache word is canceled such that the results of any pre-decoding or decoding are eliminated from the processor pipeline, and the instruction is not executed. The processor further halts the processor pipeline and obtains the desired instruction from main memory.

Late cancel method and apparatus for a high performance microprocessor

A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals. The microprocessor responds to the Bmiss signal by issuing the access onto the second bus in the event of a cache miss.

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Aloha, OR, United States of America

Phillip G Lee