Motorola Corporation

Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

Phillip E Crabtree

Wei E Wu

Stanley Michael Filipiak

Hsing-Huang Tseng

Kurt H Junker

Gregory S Spencer

Massud Aminpur

Dean J Denning

Yeong-Jyh Tom Lii

Kay Hellig

David G Farber

John C Arnold

Gerald A Martin

A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Method of making a die with recessed aluminum die pads

A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.

System for forming a semiconductor device and method thereof

A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.

Method and apparatus for monitoring wafer characteristics and/or semiconductor processing consistency using wafer charge distribution measurements

A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.

Method for manufacturing a thin oxide for use in semiconductor

A inlaid interconnect is formed in a semiconductor device (30). A first interlayer dielectric (ILD) 40 is deposited and etched to form a via opening (44). An etchstop layer (42) is deposited on ILD (40). A second ILD (45) is deposited on etchstop layer (42) in a manner so that a pinch-off region (46) is formed to prevent substantial deposition of the ILD material into via opening (44). While a small deposit (47) of ILD material may form within the via opening, this can be easily removed in a subsequent etch of ILD (45) which forms a trench opening (48) in ILD (45). A metal layer (50) is then deposited and polished to form a metal interconnect having a trench portion (52) and a via portion (54) in device (30). The present invention avoids the need for a substantial over-etch to clear the via, and avoids the need to form a thick resist mask to form the via opening, while maintaining a controlled via diameter.

Method for forming an inlaid via in a semiconductor device

Growing community of inventors

Austin, TX, United States of America

Phillip E Crabtree