Cirrus Logic Inc.

Phillip D Davis

Sudhir Sharma

Hai Long

A single chip integrated circuit 200 is disclosed which includes logic circuitry 202, memory circuitry 204, and a bus 300. First bus control circuitry 302 controls the exchange of signals between logic circuitry 202 and bus 300. Second bus control circuitry 303 controls the exchange of signals between memory circuitry 204 and bus 300. Third bus control circuitry 306 is included which controls the exchange of signals between bus 300 and at least one test pin 206. Mode control circuitry 205 is operable as control circuitry 302, 303, and 306. In the operating mode, mode control circuitry 205 activates first bus control circuitry 302 and second bus control circuitry 303. In a memory test mode, mode control circuitry 205 activates second bus control circuitry 303 and third bus control circuitry 306 and deactivates first bus control circuitry 302. In a logic test mode, test mode circuitry 205 activates first bus control circuitry 302 and third bus control circuitry 306 and deactivates second bus control circuitry 303.

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Lewisville, TX, United States of America

Phillip D Davis