Ltx Corporation

Verigy (singapore) Pte. Ltd.

Inovys Corporation

Phillip D Burlison

David Menis

Mark E Deome

Tommie Edward Berry

Christopher Joel Hannaford

David W Curry

Eric H Rosenfeld

Kenneth J Lanier

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Michael Carlyle Davis

John Frediani

Jason Doege

William R DeHaven

Donald Vick Organ

Victor Pogrebinsky

Mei-Mei Su

Richard C Dokken

Gerald Chan

Michael Gordon Davis

Harold S Vitale

As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.

Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test

A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.

System and method for device performance characterization in physical and logical domains with AC SCAN testing

A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

Dynamic mask memory for serial scan testing

An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.

Apparatus for locating a defect in a scan chain while testing digital logic

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.

Dynamically reconfigurable precision signal delay test system for automatic test equipment

A single memory automated test equipment (ATE) system having multiple pin segments with dynamic pin reallocation. Each pin segment having a length 2n is coupled to the single memory by a parallel in/parallel out shift register that also has a length 2n. The single memory is used to store both parallel data vectors and serial data vectors. Each output of the shift register is coupled to one pin of the corresponding pin segment. Selected, e.g., every other output of the shift register is also coupled to a data selection circuit associated with each pin of the pin segment. The contents of the shift register may be divided into a number of equal length serial data streams. The data selection circuit provides for coupling any serial data stream from the shift register to any pin within the pin segment, and for coupling a single serial data stream to more than one pin.

System for dynamic re-allocation of test pattern data for parallel and serial test data patterns

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

High speed I.sub.DDQ monitor circuit

An apparatus for a test system for testing an electronic circuit. The apparatus includes an interconnect path, a comparator, a programmable apparatus, a first Schottky diode, and a second Schottky diode. The interconnect path has a first end and a second end. The first end of the interconnect path is coupled to the electronic circuit under test. The interconnect path transmits a signal from the electronic circuit under test to the second end of the interconnect path. The comparator is coupled to the second end of the interconnect path for receiving and comparing the signal from the electronic circuit under test with a reference voltage. The comparator has a high input impedance. The comparator provides an output signal to the test system. The programmable apparatus provides a selectable first voltage and a selectable second voltage. A first Schottky diode is provided for reducing ringing of the signal from the electronic circuit under test. A first end of the first Schottky diode is coupled to the interconnect path at a point near the comparator. A second end of the first Schottky diode is coupled to the selectable first voltage. A second Schottky diode is provided for reducing ringing of the signal from the electronic circuit under test. A first end of the second Schottky diode is coupled to the selectable second voltage. The second end of the second Schottky diode is coupled to the interconnect path at a point near the comparator.

Growing community of inventors

Morgan Hill, CA, United States of America

Phillip D Burlison