Sarnoff Corporation

Sarnoff Europe

Other

Sarnoff Europe Bvba

Rca Inc.

Phillip Czeslaw Jozwiak

John Armer

Markus Paul Josef Mergens

Cornelius Christian Russ

Koen Gerard Maria Verhaege

Bart Keppens

Cong-Son Trinh

Russell Mohn

Benjamin Van Camp

Richard N Brown

Frederic Marie Dominique De Ranter

A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.

Two-dimensional silicon controlled rectifier

An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.

Electrostatic discharge (ESD) protection device with simultaneous and distributed self-biasing for multi-finger turn-on

A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Method and apparatus for protecting a gate oxide using source/bulk pumping

An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

Electrostatic discharge protection structures having high holding current for latch-up immunity

An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.

Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies

An ESD protection circuit for a semiconductor integrated circuit (IC) having protected circuitry, includes an SCR having at least one finger. Each finger includes a PNP transistor and an NPN transistor, where an emitter of the PNP and NPN transistors is respectively coupled between an I/O pad of the IC and ground, a base of the PNP transistor being coupled to a collector of the NPN transistor, and a base of the NPN transistor being coupled to a collector of the PNP transistor. The NPN transistor of each finger further includes a first gate for triggering said finger. A PMOS transistor includes a source and a drain respectively coupled to the I/O pad of the IC and the first gate of the NPN transistor. Further, a gate of the PMOS transistor is coupled to a supply voltage of the IC.

An electrostatic discharge (ESD) protection device having a silicon controlled rectifier (SCR) for protecting circuitry of an integrated circuit (IC). The SCR includes a N-doped layer disposed over a substrate and a first P doped region disposed over the N-doped layer. At least one first N&plus; doped region forming a cathode is disposed over the P-doped region and coupled to ground. The at least one first N&plus; doped region, first P-doped region, and N-doped layer form a vertical NPN transistor of the SCR. A second P doped region forming an anode is coupled to a protected pad. The second P doped region is disposed over the N-doped layer, and is laterally positioned and electrically isolated with respect to the first P doped region. The second P doped region, N-doped layer, and first P doped region form a lateral PNP transistor of the SCR.

Electrostatic discharge protection silicon controlled rectifier (ESD-SCR) for silicon germanium technologies

A multi-finger electro-static discharge (ESD) protection circuit has at least two first resistive channels defining input fingers. At least two field effect transistor (FET) channels, each having a drain and source are connected to corresponding ones of the at least two input fingers. The gate terminals of at least one of the at least two FETs are configured to be biased by an ESD potential applied to the drain electrodes to reduce the turn-on potential of the ESD device. At least two second resistive channels are connected between a corresponding one of the source terminals of the at least two FETs and a circuit return path.

Multi-finger current ballasting ESD protection circuit and interleaved ballasting for ESD-sensitive circuits

A method of precisely controlling the thickness of dielectric islands on a substrate is provided. The subject method comprises forming a patterned layer of an etchable metal over a first dielectric layer on a substrate, forming a second layer of dielectric material thereover so that there is contact where the etchable metal layer has been removed, patterning the second dielectric layer so that islands remain only over the openings in the etchable layer, removing the etchable metal layer and then patterning the first dielectric layer. There are thus provided islands of dielectric material on the substrate having a thickness equal to the first only or the first and second dielectric layers together, respectively. The process may be extended to form at least one additional layer of dielectric material on certain of the islands.

Growing community of inventors

Plainsboro, NJ, United States of America

Phillip Czeslaw Jozwiak