Gte Laboratories Incorporated

Phillip Andrade

Michael Cooperman

Richard W Sieber

An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory. When a match is found in said content addressable memory, the cell of data from the associated address in said random access is read out to its output destination port under control of said content addressable memory.

ATM shared memory switch with content addressing

Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The MOS transistors of the first inverter circuit of the series are approximately three times larger than the MOS transistors of the same type in subsequent inverter circuits of the series. The ECL input is to the gate of the N-type transistor of the first inverter circuit. A threshold control input is connected to the gate of the P-type transistor of the first inverter circuit. This configuration increases the operating speed of the first inverter circuit and permits controlling the threshold voltage in order to stabilize the output duty cycle.

CMOS logic circuitry providing improved operating speed

Electrical circuitry for changing the operating voltage conditions of CMOS inverter circuitry so as to shift its threshold voltage in a direction to cause the duty cycle of the output signals to equal the duty cycle of the input signals. An average filtered DC output voltage from the inverter circuitry is used as a control signal to a variable voltage supply which changes the operating voltages, thus shifting the threshold level of the inverter circuitry.

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Lexington, MA, United States of America

Phillip Andrade