International Business Machines Corporation

Phillip A Senum

Steven Michael Douskey

Michael John Hamilton

Amanda Renee Kaufer

A method and circuit for implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG), and a design structure on which the subject circuit resides are provided. A random fault is selected in the design. A test pattern is generated and applied the test pattern to a design under test to test the selected random fault. The test is re-simulated to determine faults that are covered by the applied test pattern. A next iteration of test pattern generation includes selecting a fault that is based upon the previous test pattern generation for generating new test patterns.

Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through scan skewing

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

Implementing register array (RA) repair using LBIST

A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in On Product Multiple Input Signature Register (OPMISR) testing through spreading in a stump mux data chain structure, and a design structure on which the subject circuit resides are provided. The stump mux chain structure includes a plurality of stump muxes connected in series by a respective rotation function. A respective exclusive OR (XOR) spreading function included with each of the plurality of stump muxes provides channel inputs. XOR inputs are applied to each XOR spreading function providing unique input combinations for each respective channel included with each of said plurality of stump muxes. The respective rotation function enables test data to be rotated as scan data enters each stump mux to further make the test data unique for each stump mux.

Implementing decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) through spreading in stumpmux daisy-chain structure

A method and circuit are provided for implementing enhanced scan data testing for test time reduction and decreased scan data interdependence with on product multiple input signature register (OPMISR++) testing, and a design structure on which the subject circuit resides. A respective Pseudo-Random Pattern Generator (PRPG) provides channel input patterns to a respective associated scan channel used for the OPMISR++ diagnostics. Control inputs are coupled to the Pseudo-Random Pattern Generator (PRPG) providing PRPG control distribution. The PRPG selectively provides controlled channel input patterns for the respective scan channel responsive to the control inputs.

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Rochester, MN, United States of America

Phillip A Senum