Bull S.a.

Philippe Vallet

Laurent Ducousso

Christian Bernard

Annie Vinot

Monika Obreska

Marie-Odile Lamarche

Hubert Franzetti

Thierry Dolidon

A data processing system having processors with large instruction sets comprises a plurality of microprogrammed execution units (EAD, BDP, FPP), which communicate with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BOP). A third unit is a floating point calculation unit (FPP). To permit the units to function autonomously, each unit includes its own command block and synchronizing means to authorize or interrupt the execution of the microprogram defined by the instruction in progress in each unit. These synchronizing means interrupt said execution if: either an operand contained in said memory means (CA) and necessary for said execution is not effectively received by said unit, or a result expected by said unit and calculated by another unit is not effectively received by said unit, or a result calculated in said unit cannot be effectively transmitted to the unit or to the memory means intended to receive said result.

Processor with multiple microprogrammed processing units

A data processing system having processors with large instruction sets optimized for the execution of brief instructions. The processor (CPU) comprises a plurality of microprogrammed execution units (EAD, BDP, FPP) communicating with one another and with a memory (MU) by way of a cache memory (CA). One of the units is an addressing unit (EAD). A second unit is a binary and a decimal calculation unit (BDP). A third unit is a floating point calculation unit (FPP) to permit the units to function autonomously, each unit includes its own command block and synchronizing means, for authorizing or interrupting the execution of the microprogram defined by the instruction in progress in said unit. Each command block includes means for commanding instructions for triggering the execution of the microprogram of the first instruction in standby. The last microinstruction includes an end-of-microprogram indicator, and for certain units an anticipation indication, to condition the command means so as to authorize the execution of the microprogram of the instruction in standby before a preceding instruction has been fully completed.

Processor with a plurality of microprogrammed units, with anticipated

A device for fast memory access in a computer system that employs a high-speed associative memory for storing extracts that each include an address and an associated information element. Each extract is associated with a presence flip-flop and a reference flip-flop, their respective states being changed when an extract is used. The device according to the invention is designed to operate using two clock phases. During a first clock phase, the device compares an address to be translated with each address contained in the high-speed associative memory, evaluates a saturation condition, and latches the result of this evaluation. During the second clock phase, the device updates reference indicators as a function of the coincidence signals which are latched during the first phase and of the latched evaluation signal. The invention can be used in conjunction with cache memories and for translation of virtual addresses to real addresses.

Cache memory utilizing a two-phase synchronization signal for

A method and apparatus for fast memory access in a computer system employing a high-speed associative memory for storing extracts that each include an address and an associated information component. Each extract is associated with a presence indicator and a reference indicator, their respective states being changed when an extract is used. According to the method of the invention, the state of each reference indicator can be changed only if the number of extracts present is at least equal to a threshold value. The invention also relates to apparatus for implementing the method. The invention can be applied to cache memories and to translations of virtual addresses to real addresses.

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Lardy, France

Philippe Vallet