Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Centre National De La Recherche Scientifique

Institut National De La Sante Et De La Recherche Medicale

Université´ D'aix-Marseille

Stmicroelectronics Gmbh

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Stmicroelectronics (grenoble 2) Sas

Institut National De La Recherche Agronomique (inra)

Institut Jean Paoli & Irène Calmettes

Stmicroelectronics (rousset) Sas

Philippe Roche

Sylvain Clerc

François Jacquet

Francois Jacquet

Fady Abouzeid

Gilles Gasiot

Jean-Marc Daveau

Sébastien Combes

Yves Collette

Iuliia Voitovich

Xavier Morelli

David C McClure

Richard Ferrant

Mark A Lysinger

Bastien Giraud

Mehdi Zamanian

Jean-Philippe Noel

Yvain Thonnart

Jean Louis Denarie

Didier Fuin

Fabienne Chantal Maillet

Patrice Lerouge

Dimitri Soussan

Victor Malherbe

Jean-Francois Hugues

Jean-Claude Adrien Prome

Fabian Firmin

Martin Cochet

Brigitt Raux

Catherine Faucher

Stéphanie Betzi

Capucine Lecat-Mathieu De Boissac

Georges Truchet

Stéphane Betzi

Laurent Hoffer

Adrien Lugari

Brigit Raux

Jean-Claude Guillemot

Sabine Milhas

Jean-Jacques De Jong

This invention relates to xanthine derivative compounds that are inhibitors of BET bromodomains proteins, the method of preparation thereof and applications thereof. 

Xanthine derivative inhibitors of BET proteins

The present invention relates to a compound having the following formula (I): (I) wherein: &#x2014;R is a (C-C)alkyl group; &#x2014;R&#x2033; is preferably H; &#x2014;Ar is a (C-C)arylene radical; &#x2014;Xis &#x2014;C(&#x2550;O)&#x2014;or &#x2014;SO&#x2014;; and &#x2014;R' is chosen from the group consisting of possibly substituted (C-C)alkyl, heteroaryl, (C-C)aryl, and (hetero)cycloalkyl groups, or a pharmaceutically acceptable salt and/or tautomeric form thereof, or its racemates, diastereomers or enantiomers. 

Xanthine derivatives and uses thereof as inhibitors of bromodomains of BET proteins

Absorbed ionizing particles differentially effect first and second acquiring circuit stages configured to respectively generate first and second acquisition signals. Each acquisition signal has a characteristic that is variable as a function of an amount of absorbed ionizing particles. A measuring circuit generates, on the basis of the first and second acquisition signals, a relative parameter indicative of a relationship between the variable characteristics. A computation of a total ionizing dose is made using a 1st- or 2nd-degree polynomial relationship in the relative parameter.

Device for measuring doses of ionizing particles

A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

Measurement of the duration of a pulse

A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

Method for managing the operation of a test mode of a logic component with restoration of the pre-test state

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference ('BGPD') of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Method for controlling an integrated circuit

A method for managing operation of a logic component is provided, with the logic component including a majority vote circuit and an odd number of flip-flops equal to at least three. The method includes, following a normal operating mode of the logic component, placing a flip-flop in a test mode, and injecting a test signal into a test input of the flip-flop being tested while a logic state of the other flip-flops is frozen. A test signal output is analyzed. At the end of the test, the logic component is placed back in the normal operating mode. The majority vote circuit restores a value of the output signal from the logic component that existed prior to initiation of the test.

Method for managing the operation of a circuit with triple modular redundancy and associated device

A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.

Method for protecting a logic circuit against external radiation and associated electronic device

A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.

Read boost circuit for memory device

A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

SRAM memory cell protected against current or voltage spikes

An embodiment of the invention relates to a circuit for distributing an initial signal, comprising an input node receiving the initial signal, a plurality of terminal nodes each providing at least one resulting signal to a circuit component, and different connection branches between the input node and the plurality of terminal nodes, to which a plurality of intermediate nodes is connected, wherein connection branch is duplicated, so that each node among the input node and the intermediate nodes comprises two inputs and two outputs allowing double propagation of the initial signal towards the terminal nodes through duplicated connection branches, each terminal node terminal node receiving two input signals, images of the initial signal and providing the resulting initial signal:

Circuit for distributing an initial signal with a tree structure, protected against logic random events

A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages

A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Logic cell protected against random events

The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.

Multivibrator protected against current or voltage spikes

Growing community of inventors

Le Versoud, France

Philippe Roche