Altera Corporation

Intel Corporation

Philippe Molson

Tony San

Jeffrey Orion Pritchard

Jordan Plofsky

David James Lau

Francois Pequillat

James Loran Ball

Jarrod Colin James Blackburn

Jesse Kempa

Christopher D Finan

Harry Nguyen

Jeffrey Fox

Cora Lynn Mau

Michael Chen

Maria D'Souza

Kenny Au

Adam Schott Riggs

A test system is provided for performing design for debug (DFD) operations. The test system includes a host processor coupled to an auxiliary device. The auxiliary device includes a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary device further includes a circuit under test (CUT) and a hardened DFD hub that is controlled by the host processor via the protocol interface block. The DFD hub includes a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor directs the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub is fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.

Methods and apparatus for performing design for debug via protocol interface

One embodiment relates to an integrated circuit for a multiple-channel direct memory access system. The integrated circuit includes multiple direct memory access (DMA) controllers, each one corresponding to a different DMA channel. A channelizer receives descriptors from the DMA controllers. Fragmentation circuits in the channelizer fragment descriptors to generate multiple sub-descriptors therefrom, and the sub-descriptors may be sorted into priority queues. Another embodiment relates to a method of providing DMA transfers for multiple DMA channels using an integrated circuit. Another embodiment relates to a system for multiple-channel direct memory access. Other embodiments and features are also disclosed.

Apparatus and methods for multiple-channel direct memory access

Interface circuitry is provided to control the flow of data transmitted over a high-speed serial link. The interface circuitry may receive data over a high-speed serial link and store the received data in a receive buffer. The receive buffer may be connected to an additional buffer in an application layer module. The application layer module may produce credits based on the processing capacity of the additional buffer and send those credits to the interface circuitry. The interface circuitry may then send these credits over the high speed link.

High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry

Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

High-level language code sequence optimization for implementing programmable chip designs

Systems and methods for implementing partial reconfiguration on an integrated circuit (IC) are provided. During runtime, certain configuration changes may be implemented. The embodiments described herein allow for partial reconfiguration updates to be driven via an independent pathway, reducing complex arbitration, freeing additional application memory resources, and enabling customized partial reconfiguration logic.

Partial reconfiguration using configuration transaction layer packets

One embodiment relates to an integrated circuit with a modular direct memory access system. A read data mover receives data obtained from a source address, and a write data mover for sends the data to a destination address. A descriptor controller provides the source address to the read data mover and the destination address to the write data mover. Another embodiment relates to a method of providing direct memory access. Another embodiment relates to a system which provides direct memory access. Other embodiments and features are also disclosed.

Modular direct memory access system

Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.

DSP design system level power estimation

Various high-level languages are used to specify hardware designs on programmable chips. The high-level language programs include pointer operations that may have same iteration and future iteration dependencies. Single loop iteration pointer dependencies are considered when memory accesses are assigned to clock cycles. Multiple loop iteration pointer dependencies are considered when determining how often new data can be entered into the generated hardware pipeline without causing memory corruption. A buffer can be used to forward data from a memory write to a future read.

Scheduling optimization of aliased pointers for implementation on programmable chips

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware IO, or a random failure of some type. Suitable hardware fabrication and/or augmentation also may be used to differentiate between the prototype and production manners of operation.

Method and apparatus for providing protected intellectual property

An electronic design automation system merges embedded logic analyzer technology with system level design and analysis technology. Embedded logic analyzers provide hardware to allow board-level signal capture and subsequent analysis of test devices programmed with a hardware design generated using electronic design automation. System level environments provide interactive tools for entering, modeling, simulating and analyzing multi-domain systems such as DSP designs. Typically, a user enters a system level design as a block diagram, including embedded logic analyzer blocks. The user inserts such blocks at nodes in the design where he or she wishes to capture signals to verify the design.

Embedded logic analyzer functionality for system level environments

A method, apparatus and a filter compiler system for building a filter is disclosed. The filter compiler system includes a filter resource estimator. The filter resource estimator is configured to estimate an implementation cost of the filter. The filter compiler system determines whether the implementation cost is acceptable and updates a design of the filter upon determining that the implementation cost is unacceptable.

Growing community of inventors

San Jose, CA, United States of America

Philippe Molson