Nxp B.v.

Koninklijke Philips Corporation N.v.

Interuniversitair Microelektronica Centrum (imec)

Interuniversitair Micro-elektronica Centrum Vzw

Imec

Philippe Meunier-Beillard

Erwin Hijzen

Johannes J T M Donkers

Johannes Josephus Theodorus Marinus Donkers

Tony Vanhoucke

Hans Mertens

Wibo Daniel Van Noort

Johannes Donkers

Jan Sonsky

Bartlomiej Jan Pawlak

Matty Caymax

Prabhat Agarwal

Sebastien Nuttinck

Francois Neuilly

Joost Melai

Mathieu Rosa Jozef Caymax

Jan Willem Slotboom

Andreas Hubertus Montree

Roger Loo

Gerhard Koops

Stefaan Van Huylenbroeck

Guillaume Boccardi

Hendrik G A Huizing

Christelle Rochefort

Raymond James Duffy

Claire Ravit

Mathieu Caymax

Petrus Magnee

Andreas M Piontek

Mark C J C M Kramer

Li Jen Choi

Romain Delhougne

Greja J A M Verhelijden

Godfridus Adrianus Maria Hurkx

Erwin Hujzen

Giberto Curatola

Hijzen Erwin

Melai Joost

A bipolar transistor is fabricated having a collector () in a substrate () and a base () and an emitter () formed over the substrate. The base has a stack region () which is laterally separated from the emitter () by an electrically insulating spacer (). The insulating spacer () has a width dimension at its top end at least as large as the width dimension at its bottom end and forms a &#x393;-shape or an oblique shape. The profile reduces the risk of silicide bridging at the top of the spacer in subsequent processing, while maintaining the width of emitter window.

Spacer formation in the fabrication of planar bipolar transistors

A method of manufacturing a structure (), the method comprising forming a cap element () on a substrate (), removing material () of the substrate () below the cap element () to thereby form a gap () between the cap element () and the substrate (), and rearranging material of the cap element () and/or of the substrate () to thereby merge the cap element () and the substrate () to bridge the gap ().

Sealing structure and method of manufacturing the same

A semiconductor device () comprising a bipolar transistor and a field effect transistor within a semiconductor body () comprising a projecting mesa () within which are at least a portion of a collector region (and) and a base region () of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity () provided in the collector region (and). The base region () is narrower in the plane of the substrate than the collector region (and) due to a second insulating cavity () provided around the base region () and between the collector region (and) and the emitter region (). By blocking diffusion from the base region the first insulating cavity () provides a reduction in the base collector capacitance and can be described as defining the base contact.

Semiconductor device and method of manufacture thereof

A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; depositing a boron-doped further silicon layer over the resultant structure; forming dielectric spacers on the trench sidewalls; filling the trench with emitter material; exposing polysilicon regions outside the trench side walls by selectively removing the sacrificial layer; implanting boron impurities into the exposed polysilicon regions to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities.

Method of manufacturing heterojunction bipolar transistor and heterojunction bipolar transistor

A method of manufacturing a MEMS device comprises forming a MEMS device element (). A sacrificial layer () is provided over the device element and a package cover layer () is provided over the sacrificial layer. The sacrificial layer is removed using at least one opening () in the cover layer and the at least one opening () is sealed by an anneal process.

MEMS devices

A semiconductor device () comprising a bipolar transistor and a fieldeffect transistor within a semiconductor body () comprising a projecting mesa () within which are at least a portion of a collector region (and) and a base region () of the bipolar transistor. The bipolar transistor is provided with an insulating cavity () provided in the collector region (and). The insulating cavity () may be provided by providing a layer () in the collector region (), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer () to provide the cavity using the access path. The layer () provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity () provides a reduction in the base collector capacitance and can be described as defining the base contact.

Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (), a layer () of semiconductor material, a first insulating layer (), and a second insulating layer () which is selectively etchable with respect to the first insulating layer. A trench () is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion () therethrough. A window () is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () comprising a bipolar transistor with in that order a collector region (), a base region (), and an emitter region (), wherein the semiconductor body comprises a projecting mesa () comprising at least a portion of the collector region () and the base region (), which mesa is surrounded by an isolation region (). According to the invention, the semiconductor device () also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (), and a gate region (), which gate region () forms a highest part of the field effect transistor, and the height of the mesa () is greater than the height of the gate region (). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Semiconductor device and method of manufacturing such a device

Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer () and a sacrificial layer () on a mono-crystalline silicon substrate surface (); patterning the first stack to form a trench () extending to the substrate; depositing a silicon layer () over the resultant structure; depositing a silicon-germanium-carbon layer () over the resultant structure; selectively removing the silicon-germanium-carbon layer () from the sidewalls of the trench (); depositing a boron-doped silicon-germanium-carbon layer () over the resultant structure; depositing a further silicon-germanium-carbon layer () over the resultant structure; depositing a boron-doped further silicon layer () over the resultant structure; forming dielectric spacers () on the sidewalls of the trench (); filling the trench () with an emitter material (); exposing polysilicon regions () outside the side walls of the trench by selectively removing the sacrificial layer () of the first stack; implanting boron impurities into the exposed polysilicon regions () to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities. A HBT formed by this method is also disclosed.

The invention relates to a method of manufacturing a semiconductor device () with a substrate () and a semiconductor body () which is provided with at least one bipolar transistor having an emitter region (), a base region () and a collector region (), wherein in the semiconductor body () a first semiconductor region () is formed that forms one () of the collector and emitter regions () and on the surface of the semiconductor body () a stack of layers is formed comprising a first insulating layer (), a polycrystalline semiconductor layer () and a second insulating layer () in which stack an opening () is formed, after which by non-selective epitaxial growth a further semiconductor layer () is deposited of which a monocrystalline horizontal part on the bottom of the opening () forms the base region () and of which a polycrystalline vertical part (A) on a side face of the opening () is connected to the polycrystalline semiconductor layer (), after which spacers (S) are formed parallel to the side face of the opening () and a second semiconductor region () is formed between said spacers (S) forming the other one () of the emitter and collector regions (). According to the invention the above method is characterized in that before the further semiconductor layer () is deposited, the second insulating layer () is provided with an end portion (A) that viewed in projection overhangs an end portion (A) of the underlying semiconductor layer (). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.

Method of manufacturing a semiconductor device and semiconductor device obtained with such a method

The invention relates to a semiconductor device () with a substrate () and a semiconductor body () of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region () of a metallic material that is connected to a conductive region () of a metallic material sunken from the surface of the semiconductor body (), by which the buried conductive region () is made electrically connectable at the surface of the semiconductor body (). According to the invention, the buried conducting region () is made at the location of the active region (A) of the semiconductor body (). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention. Such a buried low resistance offers substantial advantages both for a bipolar transistor and for a MOS transistor.

Semiconductor device with low buried resistance and method of manufacturing such a device

The invention relates to a semiconductor device with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region comprises a mixed crystal of silicon and germanium, the base region is separated from the emitter region by an intermediate region of silicon having a doping concentration which is lower than the doping concentration of the emitter region and with a thickness smaller than the thickness of the emitter region, and the emitter region comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region remote from the intermediate region.

Semiconductor device with a bipolar transistor and method of manufacturing such a device

The invention relates to the manufacture of an epitaxial layer, with the following steps: providing a semiconductor substrate; providing a Si&#x2014;Ge layer on the semiconductor substrate, having a first depth; &#x2014;providing the semiconductor substrate with a doped layer with an n-type dopant material and having a second depth substantially greater than said first depth; performing an oxidation step to form a silicon dioxide layer such that Ge atoms and n-type atoms are pushed into the semiconductor substrate by the silicon dioxide layer at the silicon dioxide/silicon interface, wherein the n-type atoms are pushed deeper into the semiconductor substrate than the Ge atoms, resulting in a top layer with a reduced concentration of n-type atoms; removing the silicon dioxide layer; growing an epitaxial layer of silicon on the semiconductor substrate with a reduced outdiffusion or autodoping.

Method of producing an epitaxial layer on semiconductor substrate and device produced with such a method

Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench () formed on a silicon substrate () having opposed silicon oxide side walls (); selectively growing a highly doped mono-crystalline layer () on the silicon substrate in the trench; and non-selectively growing a silicon layer () over the trench in order to form an amorphous polysilicon layer over the silicon oxide sidewalls.

Method for fabricating a mono-crystalline emitter

Consistent with an example embodiment, there is a bipolar transistor with a reduced collector series resistance integrated in a trench of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region with a first part on a selected portion of the collector region (), which is on the bottom of the trench, and an emitter region on a selected portion of the first part of the base region. A base contact electrically contacts the base region on a second part of the base region, which is on an insulating region. The collector region is electrically contacted on top of a protrusion with a collector contact.

Growing community of inventors

Kortenberg, Belgium

Philippe Meunier-Beillard