Intel Corporation

Philippe Matagne

Jack T Kavalieros

Robert S Chau

Brian S Doyle

Matthew V Metz

Mark L Doczy

Suman Datta

Justin K Brask

Martin D Giles

Been Y Jin

Everett X Wang

Mark Stettler

Lucian Shifren

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form SiGe. The highest layer may be of the form SiGeon the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form SiGeon the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Growing community of inventors

Beaverton, OR, United States of America

Philippe Matagne