International Business Machines Corporation

Philippe Mark Vereecken

Hariklia Deligianni

Panayotis Constantinou Andricacos

Cyril Cabral, Jr

Katherine Lynn Saenger

Sandra Guy Malhotra

Emanuel Israel Cooper

Michael Wayne Lane

Keith Thomas Kwietniak

Veeraraghavan S Basker

Soon-Cheon Seo

Kenneth Parker Rodbell

Martin Michael Frank

John Michael Cotte

Conal Eugene Murray

Vamsi Krishna Paruchuri

Rajarao Jammy

Carlos Juan Sambucetti

Shyng-Tsong Chen

Fenton Read McFeely

Mahadevaiyer Krishnan

Darryl D Restaino

Xiaoyan Shao

Robert Rosenberg

Erick G Walton

Wei-Tsu Tseng

Wilma Jean Horkans

Peter Stevens Locke

Stefanie Ruth Chiras

James Edward Fluegel

Dean S Chung

Fenton Reed Mc Feely

In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping .

Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

Void-free damascene copper deposition process and means of monitoring thereof

A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Selective capping of copper wiring

A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Method for electroplating on resistive substrates

Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

Field effect transistor with electroplated metal gate

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Sleepy Hollow, NY, United States of America

Philippe Mark Vereecken