International Business Machines Corporation

Imec Vzw

Imec

Katholieke Universiteit Leuven

Ebara Corporation

Nederlandse Organisatie Voor Toegepast-natuurwetenschappelijk Onderzoek Tno

Panasonic Holdings Corporation

King Abdulaziz City for Science and Technology

Universiteit Hasselt

Philippe M Vereecken

Hariklia Deligianni

Cyril Cabral, Jr

Xiaoyan Shao

Sandra Guy Malhotra

Stephen Mark Rossnagel

Anna Wanda Topol

Emanuel Israel Cooper

Randolph F Knarr

Katherine Lynn Saenger

Stanislaw Piotr Zankowski

Veeraraghavan S Basker

Martin Michael Frank

John Michael Cotte

Conal Eugene Murray

Vamsi Krishna Paruchuri

Koji Mishima

Rajarao Jammy

Shyng-Tsong Chen

Mahadevaiyer Krishnan

Panayotis Constantinou Andricacos

Junji Kunisawa

Mizuki Nagai

Hiroyuki Kanda

Hidekazu Arase

Satoru Yamamoto

Dirk De Vos

Wei-Tsu Tseng

Hidenao Suzuki

Cedric Huyghebaert

Hiroki Yabe

Geoffrey Pourtois

Shinya Morisawa

Sandeep Unnikrishnan

Keiichi Kurashina

Brett Caroline Baker-O'Neal

Maarten Mees

Akihiko Sagara

Marina Yurievna Timmermans

Kunihito Ide

Rob Ameloot

Knut Bjarne Gandrud

Ivo Stassen

Xubin Chen

Aleksandar Radisic

Marlies Van Bael

Geoffroy Hautier

Lili Deligianni

Caliopi Andricacos, Legal Representative

Sven Gielis

An Hardy

Alaa Abd-Elnaiem

Alfonso Sepulveda Marquez

Nouha Labyedh

Aleksander Radisic

At least one embodiment relates to a method for transforming at least part of a valve metal layer into a template that includes a plurality of spaced channels aligned longitudinally along a first direction. The method includes a first anodization step that includes anodizing the valve metal layer in a thickness direction to form a porous layer that includes a plurality of channels. Each channel has channel walls and a channel bottom. The channel bottom is coated with a first insulating metal oxide barrier layer as a result of the first anodization step. The method also includes a protective treatment. Further, the method includes a second anodization step after the protective treatment. The second anodization step substantially removes the first insulating metal oxide barrier layer, induces anodization, and creates a second insulating metal oxide barrier layer. In addition, the method includes an etching step.

Transforming a valve metal layer into a template comprising a plurality of spaced (nano)channels and forming spaced structures therein

A solid electrolyte of the present disclosure includes: a porous dielectric having a plurality of pores interconnected mutually; and an electrolyte including a metal salt and at least one selected from the group consisting of an ionic compound and a bipolar compound and at least partially filling an interior of the plurality of pores. Inner surfaces of the plurality of pores of the porous dielectric are at least partially modified by a functional group containing a halogen atom.

Solid electrolyte, electrode, power storage device, and method for producing solid electrolytes

At least one embodiment relates to a method fabricating a solid-state battery cell. The method includes forming a plurality of spaced electrically conductive structures on a substrate. Forming the plurality of spaced electrically conductive structures on the substrate includes transforming at least part of a valve metal layer into a template that includes a plurality of spaced channels aligned longitudinally along a first direction. Transforming at least part of the valve metal layer into the template includes a first anodization step, a second anodization step, an etching step in an etching solution, and a deposition step. The method also includes forming a first layer of active electrode material on the plurality of spaced electrically conductive structures, depositing an electrolyte layer over the first layer of active electrode material, and forming a second layer of active electrode material over the electrolyte later.

Fabrication of solid-state battery cells and solid-state batteries

An method for manufacturing a electronic device is provided having a current collector capable of a high specific charge collecting area and power, but is also achieved using a simple and fast technique and resulting in a robust design that may be flexed and can be manufactured in large scale processing. To this end the electronic device comprising an electronic circuit equipped with a current collector formed by a metal substrate having a face forming a high-aspect ratio structure of pillars having an interdistance larger than 600 nm. By forming the high-aspect structure in a metal substrate, new structures can be formed that are conformal to curvature of a macroform or that can be coiled or wound and have a robust design.

Device and method of manufacturing high-aspect ratio structures

A method for producing on-chip interconnect structures on a substrate is provided, comprising at least the steps of providing a substrate and depositing a ruthenium-comprising layer on top of said substrate, and then performing a pre-treatment of the Ru-comprising layer electrochemically with an HBF-based electrolyte, and then performing electrochemical deposition of copper onto the pre-treated Ru-comprising layer.

Pre-treatment method to increase copper island density of CU on barrier layers

A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed.

Contact metallurgy structure

The present invention relates to a method for obtaining monocrystalline or single crystal nanowires. Said nanowires are grown in a pattern making use of electro-chemical deposition techniques. Most preferred, the electrolytic bath is based on chlorides and has an acidic pH. Single element as well as combinations of two elements nanowires can be grown. Depending on the element properties the obtained nanowire can have metallic (conductive) or semi-metallic (semi-conductive) properties. The observed nanowire growth presents an unusual behavior compared to the classical nanowire template-assisted growth where a cap is formed as soon as the metal grows out of the pattern. Under given conditions of bath composition and potential (current) settings the nanowires grow out of the pattern up to a few microns without any significant lateral overgrowth.

Free standing single-crystal nanowire growth by electro-chemical deposition

A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow

A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Method of forming electrodeposited contacts

A plating apparatus securely carries out a flattening plating of a substrate to form a plated film having a flat surface without using a costly mechanism, and without applying an extra plating to the substrate. The plating apparatus includes a substrate holder; a cathode section having a seal member for watertightly sealing a peripheral portion of the substrate, and a cathode electrode for supplying an electric current to the substrate; an anode disposed in a position facing the surface of the substrate; a porous member disposed between the anode and the surface of the substrate; a constant-voltage control section for controlling a voltage applied between the cathode electrode and the anode at a constant value; and a current monitor section for monitoring an electric current flowing between the cathode electrode and the anode, and feeding back a detection signal to the constant-voltage control section.

Plating apparatus and plating method

A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

Structure for optimizing fill in semiconductor features deposited by electroplating

Structure and method of forming electrodeposited contacts

Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Selective capping of copper wiring

Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

Field effect transistor with electroplated metal gate

Growing community of inventors

Leuven, Belgium

Philippe M Vereecken