Arm Limited

Philippe Luc

Nicolas Chaussade

Florent Begon

Elodie Charra

Frederic Claude Marie Piry

Philippe Jean-Pierre Raphalen

Gilles Eric Grandou

Norbert Bernard Eugéne Lataille

A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided for receiving a block of data containing at least one data value, and for converting each data value from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first size, in order to produce re-ordered data. Second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.

Data processing apparatus and method for converting data values between endian formats

A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2) transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

Cache eviction

Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.

Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation

Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed. For a speculative pending write access request that is determined to be allowed to proceed, the attributes associated with that access request and the identifier associated with that access request are transferred from the allocated slot to a write entry within a write access buffer, after which the allocated slot is freed for allocation to a subsequent access request. When a speculative confirmed signal is then received from the device specifying that identifier, the write access buffer outputs the attributes from the write entry to store circuitry used to complete the access request. This provides a very efficient mechanism for handling speculative write accesses within a cache.

Cache circuitry, data processing apparatus and method for handling write access requests

A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information. If it is determined that the data entry should be written to the memory, the eviction logic (1) transfers the information from the eviction buffer to a bus coupled with the memory, (2)transfers data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, (3) transfers information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data portion of the eviction buffer corresponds to the first of the plurality of data entries and the information stored by the data portion of the eviction buffer corresponds to the second of the plurality of data entries, and (4) transfers the data stored by the data portion of the eviction buffer to the bus. This approach provides a low-power, high performance technique for handling eviction requests.

A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated. This enables multiple line fill requests to be simultaneously pending and subsequent line fill requests to be initiated whilst previous line fill requests are outstanding. Accordingly, subsequent line fill requests may be initiated earlier than would have been possible had the line fill buffer had to wait for all of the line fill data associated with each line fill request to be returned.

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Nice, France

Philippe Luc