Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Philippe Lance

Thierry Cassagnes

Erwan Hemon

Valerie Bernon-Enjalbert

Lianjun Liu

Arlette Marty-Blavier

Patrice Besse

David Joseph Monk

Evgueniy Nikolov Stefanov

Jean-Michel Francis Reynes

Matthijs Pardoen

Yean Ling Teo

Stephan Ollitrault

Kurt U Neugebauer

Valérie Bernon-Enjalbert

Yann Weber

Philippe Meunier

Babak A Taheri

Andre Peyre Lavigne

Michael Bairanzade

Jean-Michel Reynes

Eric Rolland

A system for programming integrated circuit (IC) dies formed on a wafer includes a magnetic field transmitter that outputs a digital test program as a magnetic signal. At least one digital magnetic sensor (e.g., Hall effect sensor) is formed with the IC dies on the wafer. The digital magnetic sensor detects and receives the magnetic signal. A processor formed on the wafer converts the magnetic signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The magnetic field transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the magnetic signal so that all of the IC dies are concurrently programmed with the digital test program.

Magnetic field programming of electronic devices on a wafer

A system for programming integrated circuit (IC) dies formed on a wafer includes an optical transmitter that outputs a digital test program as an optical signal. At least one optical sensor (e.g., photodiode) is formed with the IC dies on the wafer. The optical sensor detects and receives the optical signal. A processor formed on the wafer converts the optical signal to the digital test program and the digital test program is stored in memory on the wafer in association with one of the IC dies. The optical transmitter does not physically contact the dies, but can flood an entire surface of the wafer with the optical signal so that all of the IC dies are concurrently programmed with the digital test program.

Optical programming of electronic devices on a wafer

A chip damage detection device is provided that includes at least one bi-stable circuit having a first conductive line passing through an observed area of a semiconductor integrated circuit chip for damage monitoring of the observed area. The at least one bi-stable circuit is arranged to flip from a first stable state into a second stable state when a potential difference between a first end and a second end of the first conductive line changes or when a leakage current overdrives a state keeping current at the first conductive line. Further, a semiconductor integrated circuit device that includes the chip damage detection device and a safety critical system that includes the semiconductor integrated circuit device or the chip damage detection circuit is provided.

Chip damage detection device for a semiconductor integrated circuit

A semiconductor device arrangement comprises a semiconductor device and an injector device. The semiconductor device comprises a first current electrode region of a first conductivity type, a second current electrode region of the first conductivity type, a drift region between the first and the second current electrode regions, and at least one floating region of a second conductivity type formed in the drift region. The injector device is arranged to receive an activation signal when the semiconductor device is turned on and to inject charge carriers of the second conductivity type into the drift region and the at least one floating region in response to receiving the activation signal.

Semiconductor device and method of forming a semiconductor device

Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.

System and method for communicating on an electrical bus

An integrated circuit comprises electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to one or more external connector(s) of the integrated circuit. The ESD protection circuitry comprises at least one ESD protection component coupled to the one or more external connectors for providing ESD protection thereto. The ESD protection circuitry further comprises an ESD connector coupled to the one or more external connector(s), arranged to couple supplementary ESD protection to the one or more external connector(s).

Integrated circuit, electronic device and ESD protection therefor

A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.

Fault management for a communication bus

A bus driver has a ground terminal and a first and a second terminal. In a first operation mode the bus driver provides at the first terminal a first output voltage comprising a first data signal; and at the second terminal the bus driver provides a second output voltage comprising a second data signal. In a second operation mode the bus driver provides at the first terminal a first output voltage comprising a third data signal; and at the second terminal the bus driver provides a second output voltage, wherein a curve of the second output voltage is synchronous however inverted in relation to a curve of the first output voltage. An engine comprises a bus driver as set out above.

Flexible bus driver

A data communication system includes one or more data processing units and includes a central control unit. The decentralized data processing units are connected to the central control unit by data connection. The central control unit includes a synchronisation unit for outputting via the data connection an synchronisation signal to the data processing unit. The data processing unit includes a data generator for generating data and transmitting, after the synchronisation signal, data to the central control unit.

Data communication system and method

A system comprises a voltage regulator operably coupled to an external component, a voltage regulator reset circuit and at least one functional element supplied with a voltage by the voltage regulator. The voltage regulator reset circuit is arranged to repetitively reset the voltage regulator upon disconnection of the external component.

Regulated voltage system and method of protection therefor

A driving circuit for generating a required firing current for a safety device comprising an arrangement of a first transistor (M) connected in series with a second transistor (M); and a power control transistor (M) connected in series with the first transistor; characterised in that the first and second transistors operate in fully switched on mode (Rds(on)) and the required firing current (I(squib)) is generated by means of varying the voltage (Vc) across the gate source of power control transistor and the first and second transistors in a predetermined manner.

Digital squib driver circuit

A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.

Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal

A communication node including drivers for applying a switched signal to a communication line such as a CAN bus or a LIN bus, with a controlled slew rate. The driver comprises a series of transfer elements and a series of delay elements for cumulatively establishing operational connections of the transfer elements with the communication line, whereby to apply the switched signal progressively to the communication line. A feedback loop is responsive to the signal that the driver applies to the communication line for controlling the delays of the delay elements so as to control the delays with which the operational connections of the transfer elements with the communication line are established.

Communication apparatus including driver means for applying a switched signal to a communication line with a controlled slew rate

An apparatus for an integrated circuit comprising a thermal sensor ( ), an A-D converter ( ) coupled to the thermal sensor, wherein the thermal sensor provides an input to the A-D converter, and the A-D converter converts the input to a digital value representative of the thermal environment of the thermal sensor. The integrated circuit collects a data value at a location on an integrated circuit wherein the data value has a predetermined functional relationship to the temperature at the location. The integrated circuit converts the data value to a value representative of the thermal environment of the location on the integrated circuit.

Apparatus for managing an intergrated circuit

A protected Darlington transistor arrangement comprising: first (2) and second (4) bipolar transistors each having a base, a collector and an emitter, the base of the first transistor being coupled to the base (B) of the Darlington transistor, the collectors of the first and second transistors being coupled to the collector (C) of the Darlington transistor, the emitter of the first transistor being coupled to the base of the second transistor, and the emitter of the second transistor being coupled to the emitter (E) of the Darlington transistor; and a third bipolar transistor (6) having a base, a collector coupled to the collector of the Darlington transistor, and an emitter, wherein the Darlington transistor arrangement further comprises: a Zener diode (8) coupled between the collector of the Darlington transistor and the base of the third transistor, the base of the third transistor being coupled to the emitter of the second transistor, and the emitter of the third transistor being coupled to the base of the second transistor.

Growing community of inventors

Toulouse, France

Philippe Lance