General Electric Company

Philippe L Jacob

Glenn A Forman

Sharbel E Noujaim

John Andrew Mallick

Donald Thomas McGrath

Steven L Garverick

Joseph E Krisciunas

Steven L Gaverick

A system for processing digital electrical power signals derived from at least one externally supplied, substantially continuous, substantially alternating, electrical signal having a primary or fundamental frequency, comprises: a multiply-accumulate arithmetic processor having three input ports with at least one input port for receiving the digital electrical power signals, an output port and a processor control port; a first memory unit for storing a plurality of processor control signals; a second and third memory unit each for storing a separate plurality of processor input signals; and a memory control unit having the capability to respectively couple the first memory unit to the processor control port, and the first processor input port to one of the second and third memory units for each cycle of the primary frequency so that newly received digital electrical power signals may be continually processed by the processor for a predetermined number of cycles.

Programmable digital signal processor system for processing electrical

The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.

Subsampling time-domain digital filter using sparsely clocked output

A method for performing oversampled analog-to-digital conversion of an input signal to generate a conversion result signal essentially free of systematic errors in accordance with the invention includes the steps of: performing oversampled analog-to-digital conversion of the input signal to generate a preliminary conversion result signal accompanied by systematic error, performing oversampled analog-to-digital conversion of a zero-valued signal to generate a correction signal essentially consisting of a corresponding systematic error, and differentially combining the correction signal and the preliminary conversion result signal to generate the conversion result essentially free of systematic errors. In a structural embodiment of the invention the systematic error in an oversampled analog-to-digital converter is suppressed by subtracting from the conversion response the response of a similar oversampled analog-to-digital converter to the reference voltage as its analog input signal.

Correction of systematic error in an oversampled analog-to-digital

Instantaneous trip capability is provided to an electronic circuit breaker, which is of the type that generates trip signals by accumulating squares of power line current samples and thresholds the accumulation results. Samples of power line current are taken directly from the current transformer and analog-to-digital converter cascade generating them. The analog-to-digital converter is of an oversampling type, using a delta-sigma modulator. The samples are threshold detected against a prescribed threshold value without previous squaring, integration and detection. The threshold detector result is checked for two consecutive overcurrent indications before an instantaneous trip signal is generated.

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Clifton Park, NY, United States of America

Philippe L Jacob