International Business Machines Corporation

Cisco Technology, Inc.

Philippe Klein

Philippe Cuny

Olivier Maurel

Oliver M Maurel

Jean L Calvignac

Jean-Claude Dispensa

Ghislain Imbert De Tremiolles

Michel Paul Verhaeghe

Claude Gomez

Bernard J Naudin

Jean-Pierre Lips

Gerard Barucchi

Alexandre Jay

Jean-Luc Peter

Jean-Philippe Loison

A system for accessing a memory organized in memorization subsystems or memory blocks, e.g. standard Dual In-line Memory Modules, wherein the words to be stored are split into unitary elements so that several memorization subsystems are used to store one word and its associated Block Error Code (BEC) bits, is disclosed. The system includes a detector to detect a failure within a memorization subsystem. Insulator that are associated to each memorization subsystem insulate the failed memory block, and a new memorization subsystem is accessed in lieu of the failed one thanks to identification device which determine an available unfailed memory block. The user may replace the failed memory block without shutting down the memory device.

Memory access system

A system for housing CompactPCI cards in a frame that does not meet a specified CompactPCI form factor (3U and 6U) is presented. Existing telecommunication frames have generally a larger depth that those required by the CompactPCI standard ( mm) and therefore the insertion of CompactPCI cards ( ) cannot be performed directly into the main backplane ( ) of the frames. An intermediate backplane ( ), or so-called CompactPCI backplane, comprising six CompactPCI connectors on a front side for allowing the insertion of up to six CompactPCI adapters ( ) (3U and/or 6U), and one doubled-headed CompactPCI connector ( ) on a back side being common to one of the six front side connectors ( ) for insertion of a System Card ( ), is connected to the main frame backplane ( ) using the System Card ( ). The System Card functions as a card extender between the CompactPCI adapters ( ) and the main backplane of the frame. The depth of the System Card ( ) will be such that the depth of CompactPCI cards ( ) plus the depth of the System Card ( ) spans the full depth of the frame ( ).

System for housing CompactPCI adapters in a non-CompactPCI frame

Method for reducing the effects of signal reflections in a data communications network

Method and device for caching the IP header of a message being routed through a data transmission network wherein each node includes a route processor for computing a routing algorithm, a main memory for storing the message, a cache memory; and an IP header detection logic circuit for storing the header in the cache memory as the message is being stored in the main memory. Once the header has been stored in the cache memory, it can be read from the cache memory in order to compute the routing algorithm. The new header resulting from the routing computation is written into the cache memory and is then read from the cache memory when the message including the header and the message data is sent over the network.

Method and device for storing an IP header in a cache memory of a network node

The auto-sequenced state machine according to the present invention has a programmable state duration which is independent from the logic speed, it may be adapted to any Moore state machine and may operate in metastability occurrence of the latches (2) of the state machine. The programming of a granularity of half a clock cycle provides a performance optimization by using a system of two clocks which are in opposite phase. Moreover, the state duration may be programmable on line. The auto-sequenced state machine is composed of a basic Moore state machine to which is connected a device (16) comprising a current state decoder (15) which decodes the current state signals Q(t) from the Moore state machine in order to select one of the biphase state timers (13) and one of the state timing programming circuits (12), and an OR circuit (11) which receives the terminal counts (TC0, . . . , TC3) issued from the current selected biphase state timer and generates the final current terminal count (7) to the latches (2) of Moore state machine.

Multistage timing circuit having multiple counters in each timer for

The arbitrating method is based on the classification of the users into different categories, and the assignment to all users in a category of an identical privilege level which characterizes the interruption capability of the users in the category. A task performed by a selected user in a category can only be interrupted for granting access to the resource to a user in a category having a higher privilege level. Also a normal preference level is assigned to each user within a category, which determines the selection order of the users in the category. The privilege level of a user category combined with the preference level of each user constitutes the priority level of the user. The access to the resource is granted to a selected user having the highest priority level. If at least one user having a privilege level higher than the privilege level of the selected user, makes a request for the resource, the task of the selected user is interrupted and the interrupted user is assigned an interruption preference level which is higher than the normal preference levels of all other users in the category. A new user having the highest priority level is then selected after the resource is released by the interrupting user.

System for reassigning a higher priority to an interrupted user by

The method and apparatus for correcting one B-bit block in error in a memory organized in words comprising N B-bit blocks consist of appending to the data bits to be written into the memory words a limited number of error correction bits computed from a depopulated parity check matrix which gives the capability of only correcting one block in error and improving the memory failure rate by cyclically reading each word, correcting a block found in error if any and writing the corrected data bits with the corresponding error correction bits in place of the read word.

Method and apparatus for correction errors in a memory

Synchronization apparatus in interconnected units of a data processing system resynchronize received bits from a bus with the internal clock of the unit. The synchronization arrangement has two identical synchonization devices which alternately process received strobe pulses which are used for sampling data bits into a first register, generating a gating pulse on one output and a validation pulse on a second output. In response to the gating pulse, bits stored in the first register are transferred to a second register to be available for use by processing logic in synchronism with the internal clock signal. The synchronization devices include two parallel synchronization circuits operating in opposite phase so that the detection of one strobe pulse by one circuit: automatically disables the other one.

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La Gaude, France

Philippe Klein