Arm Limited

Philippe Jean-Pierre Raphalen

Gilles Eric Grandou

Frederic Claude Marie Piry

Richard Roy Grisenthwaite

Florent Begon

Norbert Bernard Eugene Lataille

Andrea Mascheroni

Stuart David Biles

David James Seal

Cédric Denis Robert Airaud

Geoffray Lacourba

Lee Douglas Smith

Melanie Emanuelle Lucie Teyssier

Philippe Luc

David Francis McHale

Elodie Charra

Albin Pierick Tonnerre

Rahoul Kumar Varma

Norbert Bernard Eugéne Lataille

Frederic Claude Piry

Christophe Justin Evrard

Christophe Philippe Evrard

A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Operand size control

A data processing apparatus has data processing circuitry for performing data processing operations on data, and a hierarchical cache structure for storing at least a subset of the data for access by the data processing circuitry. The hierarchical cache structure has first and second level caches, and data evicted from the first level cache is routed to the second level cache under the control of second level cache access control circuitry. Cache maintenance circuitry performs a cache maintenance operation in both the first level cache and the second level cache. The access control circuitry is responsive to maintenance indication data to modify the eviction handling operation performed in response to the evicted data, so as to cause the required cache maintenance for the second level cache to be incorporated within the eviction handling operation.

Data processing apparatus and method for handling performance of a cache maintenance operation

A data processing apparatus is provided in which a processor unit accesses data values stored in a memory and a cache stores local copies of a subset of the data values. The cache maintains a status value for each local copy stored in the cache. When the processor unit executes a load-exclusive operation, a first data value is loaded from a specified memory location and an exclusive use monitor begins monitoring the specified memory location for accesses. When the processor unit executes a store-exclusive operation, a second data value is stored to the specified memory location if the exclusive use monitor indicates that the first data value has not been modified since the load-exclusive operation was executed. When a local copy of the first data value is stored in the cache and the status value for the local copy of the first data value indicates that the processor unit has exclusive usage of the first data value, the data processing apparatus is configured to prevent modification of the status value for a predetermined time period after the processor unit has executed the load-exclusive operation.

Data processing apparatus and method for performing load-exclusive and store-exclusive operations

A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests.

Prefetching of data and instructions in a data processing apparatus

A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.

Handling of write access requests to shared memory in a data processing apparatus

Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.

Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation

Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.

Cache logic, data processing apparatus including cache logic, and a method of operating cache logic

The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access requests, each access request having associated therewith an address of a data value to be accessed. Further, the data processing apparatus has an n-way set associative cache memory operable to store data values for access by the processing unit, each way of the cache memory comprising a plurality of cache lines, and each cache line being operable to store a plurality of data values. The cache memory further comprises for each way a TAG storage for storing, for each cache line of that way, a corresponding TAG value. The cache memory is operable, when the processing unit is issuing access requests specifying data values held sequentially in a cache line of a current way of the cache memory, to perform a speculative lookup in at least one TAG storage to determine whether the TAG value associated with the next cache line in one way associated with the at least one TAG storage equals an expected tag value. If that TAG value does equal the expected tag value, and following an access request identifying a last data value in the cache line of the current way, a further access request is issued identifying the next cache line, then the cache memory is operable, without further reference to any TAG storage of the cache memory, to access from that next cache line of the one way the data value the subject of the further access request. This provides significant power savings when handling accesses to a cache memory.

Handling of cache accesses in a data processing apparatus

A data processing systemutilizes a register renaming mechanismto rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The register renaming mechanismincludes a renaming recovery unitwhich enables recovery from incorrectly executed speculative instructions by restoring the register mapping to the state prior to those incorrect instructions with the physical registers restored to containing the data values which were current at the time prior to that incorrect instruction. In the case of load instructions, these are treated as speculative but the data value returned in response to the load instruction and stored within a physical register is released for use as soon as it is returned and prior to a determination result being available as to whether or not that data value is corrupt. Corruption checking an take the form of ECC checking, parity checking and the like, and when a late error signal is generated then this indicates whether or not the data value has been properly released for use. If corruption is detected, then the renaming recovery unitis used to recover the state of the systemin a precise way to that preceding the failing load instruction.

Speculative data value usage

A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively operable to store request information indicative of a previous request and to maintain associated cache information indicating whether a cache line in a cache is currently allocated for writing data values to an address associated with that request; and entry selection logic operable to determine which one of the plurality entries to allocate to store the request using the request information and the associated cache information of the plurality of entries to determine whether a cache line in the cache is currently allocated for writing the data value to the address in memory. By reviewing the entries in the buffer logic and identifying which entry to store the request based on information currently stored by the buffer logic, the need to obtain cache information indicating whether any cache line in a cache is currently allocated for writing the data value may be obviated. In turn, the need to perform a cache look up to obtain the cache information may also be obviated. It will be appreciated that by obviating the need to perform a cache lookup, the power consumption of the store buffer may be reduced. Also, the amount of cache bandwidth consumed by performing unnecessary cache lookups may also be reduced, thereby significantly improving the performance of the cache.

Store buffer capable of maintaining associated cache information

A data processing apparatus and a method for caching data values in data processing apparatus comprising a level one cache and a level two cache is disclosed. Both the level one cache and the level two cache are operable to store the data values. The method comprises the steps of: a) receiving a transaction request in which a data transaction relating to a data value is requested to occur, the transaction request including cache policy attributes associated with an address of the data value; and b) determining from the cache policy attributes whether or not the data value can be stored by the level one cache and the level two cache and, if so, in which one of the level one cache and the level two cache the data value is to be stored in order to ensure that the data value is prevented from being stored in both the level one cache and the level two cache. Providing cache policy attributes with each data transaction enables a simple determination to be made of which cache should be used to store each data value, with other caches being prevented from storing that data value. Such an approach obviates the need to perform any complex operations in order to determine which cache should be used to store that data value. Hence, a data value may be prevented from being stored in both the level one cache and the level two cache at any one time which ensures that the level one cache and level two cache do not store duplicate data thereby increasing the likelihood of a cache hit within level one or level two for any data value.

Caching data

The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory. When employing exclusive behavior, the n-th level cache memory is operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory. This has been found to reduce the frequency of evictions of lines from the n+1-th level cache memory when employing exclusive behaviour.

Growing community of inventors

Valbonne, France

Philippe Jean-Pierre Raphalen