Synopsys, Inc.

Numerical Technologies, Inc.

Cadence Design Systems, Inc.

Philippe Hurat

Christophe Pierrat

Michael Lawrence Rieger

Michel Luc Cote

Robert M Lugg

Michel Luc C&ocirc;t&eacute;

Jeff Mayhew

Rwik Sengupta

Jeffrey E Nelson

Jac Paul P Condella

Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.

Electronic design tracing and tamper detection using automatically generated layout patterns

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value) with a new layer, or alternatively using a conventional layer (e.g. metal) with a new datatype (e.g. value), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Silicon tolerance specification using shapes as design intent markers

Design-specific attributes of a circuit (such as timing, power, electro-migration, and signal integrity) are used to automatically identify one or more regions of one or more layers in a layout of the circuit. The automatically identified regions may be provided to a manufacturing tool in GDSII by use of overlapping shapes in, or alternatively by moving existing shapes to, a different layer/datatype pair. For example, information about the automatically identified regions may be stored using a conventional datatype (e.g. value 0) with a new layer, or alternatively using a conventional layer (e.g. metal 3) with a new datatype (e.g. value 1), depending on the embodiment. The automatically identified regions contain cells and/or features (e.g. groups of shapes and/or individual shapes) whose tolerance in silicon (to be fabricated) is automatically changed from default, based on the design-specific attribute(s) and sensitivity thereto, expressed as design intent by a circuit designer.

Performing optical proximity correction (OPC) is typically done during a critical time, wherein even small delays in finishing OPC can have significant adverse effects on product introduction and/or market exposure. In accordance with one feature of the invention, sets of repeating structures in library elements and/or layout data can be identified during a non-critical time, e.g. early in cell library development, possibly years prior to the direct application of OPC to a final layout. OPC can be performed on repeating structures during this non-critical time. Later, during the critical time (e.g. during tape out), an OPC tool can use the pre-processed structures in conjunction with a chip layout to more quickly generate a modified layout, thereby saving valuable time as a chip moves from design to production.

Accelerated layout processing using OPC pre-processing

One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the simulated printed image that do not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.

Growing community of inventors

San Jose, CA, United States of America

Philippe Hurat