International Business Machines Corporation

Philippe Hauviller

Vincent Vallet

Dominique P Bonneau

Bertrand Gabillard

Alexandre Maltere

Michel Paul Verhaeghe

Christopher Ro

Disclosed herein is an improved serializer/deserializer (SERDES) circuit () having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (). To that end, a delay perturbation is added to the serial data stream at the serializer () output, typically using a variable delay (DEL) line (). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic () coupled to the DEL line and the deserializer circuit () analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data.

Characterizing jitter sensitivity of a serializer/deserializer circuit

Serializer/deserializer circuit for jitter sensitivity characterization

There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

Receiver having full signal path differential offset cancellation capabilities

A transition detection, validation and memorization (TDVM) circuit detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. Then n over sampled signals are fed into the TDVM circuit which includes a first section for detecting the transition at the positions of two consecutive sampled signals according to a specific signal processing, a second section for validating the transition position, and a third section for memorizing the validated transition position and generating a control signal that is used to recover the data.

Transition detection, validation and memorization circuit

There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G, . . . , G) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G, . . . , G) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G, . . . , G) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Sample selection and data alignment circuit

A differential sampling circuit is configured around a differential operational amplifier and is provided with a pair of switched-capacitor networks, each including an circuit block, to generate the real value of the differential input signal DC offset at each system clock cycle. During the first half cycle, the differential input signal pair (Vin+,Vin&#x2212;) is sampled and the holding capacitors in each network are charged. During the second half cycle, the differential input signal pair is sampled again and the holding capacitors are further charged. At the end of the cycle, the charges held in the holding capacitors are applied to the differential operational amplifier, so that the differential output signal is equal to the real differential input signal DC offset value.

Differential sampling circuit for generating a differential input signal DC offset

A built-in self test system for testing a clock and data recovery circuit. The present invention provides a built-in self test circuit which operates with high speed phase lock loop. The built-in circuit comprises data generating means for generating a test data byte and serializing means coupled to the data generating means for converting the test data byte into serial test data. The clock and data recovery means are coupled to the output of the serializing means for recovering the clock and test data from the serial test data. A deserializing means coupled to the output of the clock and data recovery means converts the recovered serial test data into a recovered test data byte, and analyzing means connected to the output of the deserializing means compares the recovered test data byte to the initial test data byte.

Built-in self test system and method for high speed clock and data recovery circuit

A device implemented in a N-bit digital-to-analog converter (DAC) to extend its resolution to N+P bits. The N-bit DAC comprises a resistive string 2 made of 2.sup.N resistive elements R1 to R16. MSB switches in block 10 and LSB switches in block 12, when closed in response to combinations of the N-bits provide the voltage at one of taps N1 to N16 to node M1. The device comprises a string 18 made of 2.sup.P-2 elements connected between nodes M1 and M7, additional LSB switch block 14 and additional MSB switches SW4-2, SW8-2, SW12-2 and SW16-2 which are closed in response to combinations of the N-bits to connect the string 18 across the taps of a selected resistor R1 to R16. The voltage generated at one of the taps M1 to M7 of string 18 is provided to the (N+P)-bit DAC output 20 by means of one of the switches in block 16. The main advantages of this device are that the monotonicity of the conversion is not impaired by the extension to (N+P) bits, and that it is not space consuming when integrated in a chip. Furthermore, various conversion capabilities may be provided by controlling the switch SW21 and the switches in block 16.

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Itteville, France

Philippe Hauviller