International Business Machines Corporation

Philippe Girard

Bertrand Gabillard

Michel Rivier

Carl Cederbaum

Fabrice Voisin

Patrick Mone

Dominique M Omet

Michel J Grandguillot

Christophe Degardin

Guillaume Vercasson

Michel Granguillot

A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vand an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vand to a one of the plurality of switches and each switch includes a fuse.

Bandgap reference generator utilizing a current trimming circuit

There is disclosed an improved differential amplifier () having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit () connected to said preceding stage, a buffer () and an amplification section () connected in series in the direct amplification line, a first amplifier (), a RC network (') and a second amplifier () connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block () is to respectively isolate the input signal and the feedback signal from the summing nodes (A&#x2032;,B&#x2032;) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter Sis considerably improved.

Differential amplifier with DC offset cancellation

There is disclosed an improved 2-stage large bandwidth amplifier () comprised of two stages formed by first and second bipolar transistors (Q,Q) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (V) is applied to the base of said first transistor via an input terminal (), while the output signal (V) is available at an output terminal () connected to the collector of said second transistor. A parallel feedback structure (') is provided. It consists, in a first branch, of two diodes (D,D) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (V). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

2-stage large bandwidth amplifier using diodes in the parallel feedback structure

An off chip driver circuit is adapted to output differential output signals at high speed rate and capable to drive high external loads without degradation of the output signals. Specifically the driver comprises a first differential pair of transistors having first differential input terminals to respectively receive differential input signals and having first differential output terminals to output the differential output signals. A first current source circuit is connected to a first common terminal of each transistor of the first differential pair of transistors. The current source is sized to provide a first current flow upon receiving the differential input signals. The driver further comprises at least a second differential pair of transistors having second differential output terminals connected in parallel to the first differential output terminals. The second differential pair of transistors respectively receives delayed differential input signals of the differential input signals on respective second differential input terminals. At least a second current source circuit is connected to a second common terminal of each transistor of the second differential pair of transistors. The second current source is sized to provide a second current flow upon receiving the delayed differential input signals. The output driver is designed such that the delay between the first and the at least second differential input signals and the value of the first and the at least second current flows are adjusted to control the slew rate of the differential output signals.

Output driver having controlled slew rate

Disclosed is a delay interpolator (DI) circuit (or mixer) that can be driven by digital signals. This DI circuit may be incorporated in the loop of a delay interpolator voltage controlled oscillator (DIVCO) circuit. In turn, the digital DIVCO circuit may be inserted in the loop of a phase-locked loop (PLL) circuit for total digitalization thereof. The novel digital delay interpolator circuit (23) has the base structure of the conventional analog delay interpolator circuit except in that, at the first (bottom) level, the two standard NFET input devices which are normally controlled by an analog signal (typically generated by a preceding DAC) are respectively replaced by two arrays (24A, 24B) of smaller NFET devices connected in parallel. The gate of each NFET device of the first array is driven by a bit (c0, c1, . . . ) of the true phase of the digital signal. The gate of each NFET device of the second array is driven by a bit (c0, c1, . . . ) of the complementary phase of the digital signal. For instance, in the loop of a PLL circuit, this digital signal (Sfilt) is generated by the phase detector, then filtered in a digital filter and stored in a thermometer register. As a result, the DAC is no longer necessary thereby saving significant room and energy consumption.

Digital delay interpolator circuit

A cache memory architecture having a separate redundant read bus fully dedicated to redundancy and fed by a single spare sub-array common to all memory sub-arrays of the cache memory. Redundant sense amplifiers are dotted to the redundant read bus, and normal sense amplifiers are connected to a main read bus. Normal and redundant data are valid and available at the same time at the outputs of the normal and redundant sense amplifiers. When the late select address signals become valid, then the correct information can be selected via a multiplexer provided with an INHIBIT input. The multiplexer is normally controlled by decoded signals generated by a decoder, unless redundancy is required. If redundancy is required, the information generated by the bit address comparator forces the multiplexer, via the INHIBIT input, to select the redundant read bus, instead of one read bus of the main read bus, and to output the redundant byte as the selected one.

Redundant read bus for correcting defective columns in a cache memory

A low power TTL/CMOS receiver circuit consists of four stages, each of which is, respectively, comprised of at least two complementary FET devices connected to each other in series. The various stages control each other by a variety of feedback interconnections. The use of feedback loops permits to significantly decrease the DC current in the input stage of the receiver circuit. It also realizes a substantial decrease in AC current consumption, although less significantly. Finally, delay variations between input and output signals are obtained as well as substantial improvements in the symmetry between the true and complement output signals of the receiver circuit.

Low power TTL/CMOS receiver circuit

A plurality of local address transition detector (LATD) circuits, one per address bit signal (Ai), of the type used in SRAMs to generate an on-chip clock pulse (LATDSi) that insures a correct timing of internal circuits such as sense amplifiers and address decoders that are essential for a correct READ/WRITE operation of the SRAM. According to one aspect of the invention, each LATD circuit includes: a first bipolar transistor (T1) serially connected with a first FET device (N1) forming a first branch; a second bipolar transistor (T2) serially connected with a second FET device (N2) forming a second branch. The first and second branches are connected in parallel between a first supply voltage (Vcc) and a common output node (N) connected to a circuit output terminal (30-i) where the output signal (LATDSi) generated by the LATD circuit (22-i) is available. The first and second bipolar transistors (T1, T2) are respectively driven by the address signal (Ai') and its complement (Ai') at the ECL voltage levels and the second and first FET devices are respectively driven by the address signal (Ai*' ) and its complement (Ai*') at the CMOS voltage levels. As a result of this design of the LATD circuit, the delays in critical paths in BICMOS circuits incorporating the LATD circuit may be significantly reduced relative to BICMOS circuits utilizing conventional LATD circuits.

BICMOS local address transition detection circuit

Input ECL level signals are received and converted into output CMOS level signals by input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) and is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of an input buffer circuit (20), which supplies two pairs of output signals (V1) V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The input buffer circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4 ) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4, P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.

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Corbeil-Essonnes, France

Philippe Girard