Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Koninklijke Philips Corporation N.v.

France Telecom/cnet

Philippe Gayet

Eric Granger

Jean-Pierre Schoellkopf

Michel Haond

Srdjan Kordic

Alain Inard

Joaquim Torres

Annie Tissier

Céline Roussel

Jean Galvier

Gordon Bease

A process for fabricating an integrated electrical circuit comprises the formation and then the removal of conducting inserts. Components of the electrical circuit are incorporated into insulating materials superposed on top of a substrate. The process makes it possible to provide an exclusion volume around certain components sensitive to electrostatic coupling, while giving each insulating material a planar surface at the end of a polishing step.

Process for fabricating an electrical circuit comprising a polishing step

A method for fabricating an integrated circuit. According to the method, a second dielectric layer is formed above a first dielectric layer, and holes and/or trenches are etched in the first and second dielectric layers. The holes and/or trenches are filled with metal in order to form electrical connection elements, and at least a third dielectric layer is formed. Holes and/or trenches are selectively etched in the third dielectric layer and the second dielectric layer with respect to the first dielectric layer and the elements, in order to control the depth of the etch. Additionally, there is provided an integrated circuit of the type having metallization levels separated by dielectric layers and metallized vias connecting lines of different metallization levels. The integrated circuit includes first and second metallization levels, first and second superposed dielectric layers located above the first metallization level, and a third dielectric layer located above the first and second dielectric layers. Further, at least one electrical connection element is provided in the third dielectric layer and passes through the second dielectric layer until it comes into contact with the first dielectric layer.

Integrated circuit with stop layer and associated fabrication process

An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistors

A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor substrate and the minimum width isolation region has a width less than the sum of the gate length and 2 p.

Semiconductor substrate having an isolation region

One embodiment of the invention is directed to a method of forming a metallization level of an integrated circuit including the steps of forming metal areas of a metallization level laterally separated by a first insulating layer, removing the first insulating layer, non-conformally depositing a second insulating layer so that gaps can form between neighboring metal areas, or to obtain a porous layer. The removal of the first insulating layer is performed through a mask, to leave in place guard areas of the first insulating layer around the portions of the metal areas intended for being contacted by a via crossing the second insulating layer.

Method of forming insulated metal interconnections in integrated circuits

An interconnect level includes upper and lower partial levels having respective conductive lines offset heightwise from each other. The interconnect level further includes respective dielectric portions separating adjacent conductive lines and extends above and below the conductive lines. At least one descending via connects a conductive line of the upper partial level with a lower element located below the dielectric portions of the interconnect level. The at least one descending via extends through the dielectric portions separating adjacent conductive lines of the lower partial level. At least one ascending via connects a conductive line of the lower partial level with an upper element located above the dielectric portions of the interconnect level. At least one ascending via extends through the dielectric portions separating adjacent conductive lines of the upper partial level.

Integrated circuit and associated fabrication process

The invention provides an integrated circuit containing at least a portion of a first, horizontal, conductive or semiconductive layer covered by a first electrically insulating layer. A first conductive member is vertically provided through the first electrically insulating layer in electrical contact with the first, horizontal layer. The first conductive member includes a lower, substantially cylindrical portion, and an upper portion comprising an enlarged head. An upper surface of the upper portion is substantially coplanar with an upper surface of the first electrically insulating layer. A second electrically insulating layer is deposited over the upper surface of the upper portion of the first conductive member and the upper surface of the first electrically insulating layer. A second conductive member is provided through the second electrically insulating layer.

High aspect ratio contact structure for use in integrated circuits

A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region. The isolation regions have substantially coplanar surfaces, also coplanar with an upper surface of the semiconductor substrate. The wide field isolation region has, in an upper surface, a hollow located a distance p from an interface with the upper surface of the semiconductor substrate and the minimum width isolation region has a width less than the sum of the gate length and 2p.

Method of forming planar isolation in integrated circuits

A method for determining the complete elimination of a thin layer (3) deposited on a substrate (1) includes the steps of providing on an area of the substrate (1) an optical diffraction grating (2, 2'), the thin layer deposited on the substrate also covering this diffraction grating, and the etching of the thin layer being also carried out in the area of the diffraction grating; illuminating the grating (2, 2') with a monochromatic light beam; and observing the evolution of the diffracted light during the etching of the thin layer, in order to determine the moment when the material of the thin layer is entirely removed.

Growing community of inventors

St. Vincent de Mercuze, France

Philippe Gayet