Xilinx, Inc.

Philippe Garrault

Jennifer D Baldwin

Premduth Vidyanandan

Richard J LeBlanc

Kenneth J Stickney, Jr

Carrie L Kisiday

Paul Cheng

Hari Devanath

A process is provided for creating an input/output (I/O) model. A set of logical I/O pins of an unplaced and unrouted circuit design is determined. Pin placement is determined for one or more of the logical I/O pins on device pins of a target device. An I/O pin profile for each of the logical I/O pins is determined. A plurality of I/O pin models available on the target device are input and an I/O pin model is selected from the plurality of I/O pin models for each of the logical I/O pins according to the respective I/O pin profiles. An I/O model is generated including each selected I/O pin model within the I/O model. The generated I/O model is stored in a processor readable storage medium.

Generation of input/output models

A method of creating a design-specific I/O model document can include reading a plurality of I/O pin models corresponding to available I/O pin profiles on a target device () and identifying I/O pins of the target device that are used by a circuit design (). An I/O pin profile for each I/O pin of the target device that is used by the circuit design can be determined (). An I/O pin model can be selected from the plurality of I/O pin models for each I/O pin of the target device that is used by the circuit design according to the I/O pin profiles (). The design-specific I/O model document for the circuit design can be generated by including each selected I/O pin model within the design-specific I/O model document (). The design-specific I/O model document can be output ().

Generating a design-specific input/output model document

Growing community of inventors

Saint Andre le Gaz, France

Philippe Garrault