Stmicroelectronics S.a.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics (crolles 2) Sas

Philippe Flatresse

Bastien Giraud

Jean-Philippe Noel

Matthieu Le Boulaire

Olivier Thomas

Marc Belleville

Sylvain Engels

Christophe Entringer

Alexandre Valentian

Pascal Salome

Julien Le Coz

Pascal Nouet

Nicolas L'Hostis

Vincent Liot

Bertrand Pelloux-Prayer

Florence Azaïs

Mario Casu

An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Integrated circuit comprising transistors with different threshold voltages

An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis.

Method for generating a topography of an FDSOI integrated circuit

A dynamic biasing circuit of the substrate of a MOS power transistor may include a first switch configured to connect the substrate to a current source which forward biases the intrinsic source-substrate diode of the transistor, when the gate voltage of the transistor turns the transistor on. The current source may include a stack of diodes in the same conduction direction as the intrinsic diode between the substrate and a supply voltage.

Transistor substrate dynamic biasing circuit

An IC has cells placed in a cell row having a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and an n-doped well beneath it and configured to apply a potential thereto, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and a p-doped well beneath the ground and configured to apply a potential thereto, and cells, each including a UTBOX-FDSOI pMOSFET including a ground beneath the pMOS, and a p-doped well beneath the ground and configured to apply an electrical potential to the ground, and a UTBOX-FDSOI nMOSFET including a ground beneath the nMOS, and an n-doped well beneath the ground and configured to apply a potential thereto. The cells are placed so that pMOS's of standard cells belonging to a row align along it and a transition cell including a another well and contiguous with first row standard cells thus ensuring continuity with wells of those cells.

Silicon-on-insulator CMOS integrated circuit with multiple threshold voltages and a method for designing the same

A device monitors at least one power switch which is series-mounted with a logic core between a first and a second potential. A connection point between the switch and logic core is carried to a third potential. The switch is biased by a biasing potential. The device includes a feedback control module mounted between first and second potentials which is capable of generating a set potential representative of the third potential variation. A biasing module of the power switch is mounted between the first and second potentials, and generates a biasing potential based on the set potential. The biasing potential linearly varies with the decrease of the third potential.

Device and method for power switch monitoring

A circuit for biasing the bulk of a MOS transistor, including a capacitive element connecting the bulk of the MOS transistor to a source of an voltage.

Method and device for adapting the voltage of a MOS transistor bulk

An embodiment of a protection circuit, comprising a first PNP-type bipolar transistor and a second NPN-type bipolar transistor, the base of the first transistor being connected to the collector of the second transistor and the collector of the first transistor being connected to the base of the second transistor, in which a MOS transistor is connected between the collector and the emitter of the second transistor.

Gated thyristor and related system and method

A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

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Froges, France

Philippe Flatresse