Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Philippe Delpech

Sébastien Cremer

Christophe Regnier

Jean-Christophe Giraudin

Stephane Monfray

Nathalie Revil

Michel Marty

Didier Dutartre

Vincent Arnal

Christophe Bernard

Christophe Garnier

Vincent Fiori

Eric Sabouret

Jean-Claude Oberlin

Sylvie Bruyere

Etienne Robilliart

Sebastien Gallois-Garreignot

Andréa Cathelin

Pierre Troadec

Laurent Salager

Sandra Lis

A semiconductor device may include at least one pad adjacent a top surface of the device, and a metal crack stop structure below the at least one pad. The metal crack structure may have an inner envelope and an outer envelope, and may be configured to be vertically aligned with the at least one pad so that an edge of the at least one pad is between the inner and outer envelopes.

Semiconductor device comprising a crack stop structure

The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Creation of capacitors equipped with means to reduce the stresses in the metal material of their lower structures

An integrated circuit includes at least one capacitor that is formed on a layer provided with at least one first trench. The capacitor, which is provided with a dielectric layer that separates two electrodes, conforms to the shape of the first trench, but leaves a part of the first trench unfilled. A material capable of absorbing stresses associated with the displacements of the walls of the trench is placed in the trench to fill the part of the first trench. A second trench is formed at least partly surrounding the first trench. This second trench is also at least partly filled with a material capable of absorbing stresses associated with the displacements of the walls of the second trench. A void may be included in the stress absorbing material which fills either of the first or second trenches.

Integrated circuit comprising at least one capacitor and process for forming the capacitor

A manufacturing process for a capacitor in an interconnection layer includes the following stages: Deposit of a first metallic layer (); Deposit of a first insulator layer () on the first metallic layer (); Deposit of a second metallic layer () on the first insulator layer (); Formation of an upper electrode () in the second layer metallic (); Deposit of a second insulator layer () covering the upper electrode (); Etching of the second insulator layer to form a spacer () on this first insulator layer surrounding the upper electrode (); then Formation of a lower electrode () and a dielectric () by removal of parts from the first metallic layer and insulator not covered by the upper electrode () or the spacer (); and Formation of an interconnection line (). This process allows for manufacturing capacitors with an increased performance, in a simplified fashion at lower cost and with an auto-alignment.

Method of fabricating a capacitor by using a metallic deposit in an interconnection dielectric layer of an integrated circuit

A capacitor fabricated, within an integrated circuit, has at least two capacitive trenches extending within a dielectric material. A metal layer is produced which is embedded in the dielectric material. To form the capacitor, the dielectric material is etched, with etching stopped at the metal layer so as to form the trenches. A layer of conductive material forming the lower electrode of the capacitor is then deposited at least on the sidewalls of the trenches and in contact with the metal layer. A dielectric layer is then deposited within the trenches. A layer of conductive material forming the upper electrode of the capacitor is then deposited within the trenches.

Method for fabricating an integrated circuit comprising a three-dimensional capacitor

An integrated electronic circuit with at least at least one passive electronic component and at least one active electronic component. The passive electronic component is formed within an insulating material disposed on a substrate. The active component is formed within a volume of substantially single-crystal semiconductor material disposed on top of the passive component.

Integrated electronic circuit comprising superposed components

An electronic circuit includes a substrate. A capacitor and at least one semiconductor component are supported by a surface of the substrate. A substantially planar screen, oriented parallel to the surface of the substrate and made of metallic material, is placed between the capacitor and the semiconductor component. Preferably, the semiconductor component is placed in proximity to the surface of the substrate and several superposed layers of insulating material cover the surface of the substrate and the semiconductor component. The capacitor is then placed within at least one layer of insulating material above the semiconductor component, and the screen is placed within an intermediate layer of insulating material between the layer incorporating the capacitor and the surface of the substrate.

Integrated electronic circuit comprising a capacitor and a planar interference inhibiting metallic screen

A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained

A process for producing an integrated electronic circuit that includes a capacitor comprises the formation of a stack on top of a substrate (). The stack comprises a first volume of a temporary material, a second volume () of at least one insulating dielectric and a third volume () of a first electrically conducting material. After a coating material () has been deposited on the stack, the temporary material is removed via access shafts (C, C) that are formed between a surface (S) of the circuit and the first volume. The temporary material is then replaced with a second, electrically conducting material.

Process for producing an integrated electronic circuit that includes a capacitor

A capacitor formed in a substrate including a recess dug into a substrate; a first layer of a dielectric material covering the walls, the bottom and the edges of the recess; a second layer of a conductive material covering the first layer; a third layer of a conductive or insulating material filling the recess; trenches crossing the third layer; a fourth layer of a conductive material covering the walls, the bottoms as well as the intervals between these trenches and the edges thereof; a fifth layer of a dielectric material covering the fourth layer; and a sixth layer of a conductive material covering the fifth layer.

Trench capacitor in a substrate with two floating electrodes independent from the substrate

An integrated circuit capacitor includes a substrate, a first metal electrode on the substrate, and a dielectric layer on the first metal electrode. The dielectric layer includes a homogeneous combination of at least two dielectric materials having permittivities varying in an opposite way based upon an electric field, with a proportion of each dielectric material being chosen so that the integrated circuit capacitor has a desired voltage linearity. A second metal electrode is on the dielectric layer.

Integrated capacitor with a mixed dielectric

An integrated circuit fuse is formed on a substrate by etching a polysilicon, metal or alloy layer deposited thereon to include a central region, at the end of which are zones with electrical contacts. The central region has at least two first electrically parallel arms. A zone of intersection of the first two arms forms a point for focusing a fusing current which facilitates the fusing of the fuse by increasing local current density flowing through the integrated circuit.

Integrated circuit fuse, with focusing of current

Method of manufacturing a capacitor integrated onto a silicon substrate, comprising a step of depositing a layer of first electrode, a step of depositing a layer of a dielectric material, a step of exposure of the dielectric layer to a plasma and a step of depositing a layer of second electrode. This creates the advantage of a design of capacitors with metallic electrodes having a good linearity versus voltage.

Method of manufacturing an integrated capacitor onto a silicon substrate

An integrated circuit fuse includes a substantially bar-shaped central region and zones having electrical contacts. The central region includes a thinned zone forming a weak point facilitating fusing of the fuse by increasing the local current density as compared to standard fusing conditions. The thinned zone is preferably obtained by proximity optical effect between the fuse and adjacent dummy elements.

Integrated circuit fuse with localized fusing point

A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

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Meylan, France

Philippe Delpech