Semiconductor Components Industries, LLC

Freescale Semiconductor,inc.

Philippe Debosque

Philippe Quarmeau

Cor Voorwinden

Dieter Jozef Joos

Vincent Teil

Cornelis Hermanus Voorwinden

In some aspects, a power supply system includes a plurality of power supply devices configured to be connected to an integrated circuit, where a power supply device of the plurality of power supply devices includes a voltage regulator configured to generate a rail voltage, and an internal diagnostic circuit. The internal diagnostic circuit is configured to detect activation of an enable signal to activate the plurality of power supply devices according to an activation power sequence, detect a rail violation of the activation power sequence in response to a value of the rail voltage at a first time, not satisfying a first condition defined by a voltage threshold, or at a second time, not satisfying a second condition defined by the voltage threshold. In response to the rail violation being detected, the internal diagnostic circuit is configured to activate an interrupt signal.

Power supply system for detecting a rail violation in a multi-rail sequence

A method of performing a system watchdog operation of a data processing system using a system watchdog timer includes creating an initial question, starting a timer of the system watchdog timer, receiving an initial answer and an initial data code, calculating an expected data code in response to the initial question, and comparing the initial data code to the expected data code. In response to a mismatch between the initial data code and the expected data code, a bus error signal is generated. In response to a match, the initial answer is compared to the initial question, and in response to a match between the initial answer and the initial question, the timer is reset and the initial data code is stored as a subsequent question, but in response to a mismatch, a remedial action of the data processing system is performed.

System watchdog timer for a data processing system

A Universal Serial Bus transmitter comprising a USBTXP input and a USBTXM input for receiving respective data signals, and a USBP driver and a USBM driver for applying the respective data signals to USBP and USBM wires respectively. The transmitter comprises a transmit signal generator responsive to an asserting edge of a signal at one of the USBP and USBM inputs to define a leading edge of a transmit signal (USBTXIP) and to a corresponding de-asserting edge of a signal at the other of the USBP and USBM inputs to define the subsequent trailing edge of said transmit signal (USBTXIP). Even if the duty cycles of the input signals USBTXP and USBTXM are substantially different from 50%, this does not cause unacceptable jitter of successive crossover points nor cause the crossover point voltage level to be outside the USB tolerance, centred on 50% of the voltage swings of the USBP and USBM signals.

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Toulouse, France

Philippe Debosque