Bull Sas

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Philippe Couvee

Yann Kalemkarian

Jean-Vincent Ficet

Sylvain Jeaugey

Simon Derr

Jean-Olivier Gerphagnon

Sébastien Dugue

Zoltan Menyhart

Jean-Jacques Pairault

Benoit Welterlen

Gaël Goret

Lionel Vincent

Nicolas Morey-Chaisemartin

Benoît Welterlen

Trong-Ton Pham

Saïd Derradji

Maxime Quinzin

Louis Davy

Angelo Solinas

Jordan Chicheportiche

Antoine Percher

Stéphane Martin

Mamady Nabe

Mireille Cheinet

Virginie Megy

Jean Olivier Gerphagnon

The invention relates to a method for optimizing the execution parameters of a software application on an information processing platform, consisting in iteratively optimizing said parameters at each execution of said application, in which:

Automatic and self-optimized determination of execution parameters of a software application on an information processing platform

The invention concerns a storage method for storing, on data servers (), data file (to) slices (to) from the execution of a plurality of processes (to) of one or more applications (), comprising: distributing the stored data file (to) slices (to) over different data servers (), characterized in that: this distribution is carried out in such a way that the data file (to) slices (to) likely to be subsequently accessed simultaneously by different application () processes (to) are stored on different data servers () so as to reduce the subsequent access, to each of all or part of these data servers () by too many application () processes (to) simultaneously, and in that: the determination of the data file (to) slices (to) likely to be subsequently accessed simultaneously by different application () processes (to) has been carried out, during a prior phase of executing these application () processes (to), by observing the behavior of these application () processes (to) in order to access these stored data file (to) slices (to) over time.

Data storage method and method for executing an application with reduced access time to the stored data

The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Method for optimizing memory access in a microprocessor including several logic cores upon resumption of executing an application, and computer implementing such a method

A method and device is described for saving a documentation data file intended for being displayed on a screen. The method includes subdividing the documentation data into data blocks; associating a detail level with at least one data block; and saving the data block with a level marker relating to the associated detail level, the marker intended to be compared with a desired detail level in order to display the data on the screen.

Documentation data file with detail levels

A device for indicating a rack among a plurality of racks, the rack being configured to receive a plurality of pieces of computer equipment is disclosed. In one aspect, the device comprises a communication unit configured to receive at least one signal from at least one piece of equipment of the pieces of equipment. The signal comprises information enabling a state of the piece of equipment to be determined. The device further comprises a control unit configured to determine a state of the rack based at least in part on the signal. The device further comprises a display unit for displaying a representation of the state determined by the control unit.

Device for indicating a datacenter rack among a plurality of datacenter racks

A method for monitoring the operation of an IT infrastructure including a plurality of calculation nodes, includes selecting calculation nodes for performing a calculation, performing the calculation via the selected calculation nodes, attributing, via the sequencer, a score to each one of the calculation nodes having participated in the calculation performed, with each score reflecting a difference between a measured operating parameter of the calculation node for which the score is attributed and a reference operating parameter of the calculation node for which the score is attributed, verifying the operation of the calculation nodes having participated in the calculation performed, the verification being carried out using scores attributed to the calculation nodes having participated in the calculation.

Method and sequencer for detecting a malfunction occurring in a high performance computer

A computer implemented process of encoding of at least one source file for obtaining an executable binary file that is executable by compilation of the at least one source file according to at least one instruction file, the process including: obtaining the at least one source file and the at least one instruction file; obtaining a plurality of encryption keys, at least two keys from the plurality of encryption keys being of different types, each type of encryption key being associated with a particular access right to the at least one source file; selecting each of the keys from the plurality of encryption keys and encrypting the source file according to the key selected and generating the source file encrypted according to the key selected; generating a package containing the at least one instruction file and the source files encrypted according to each key of the plurality of encryption keys.

Process and device for encoding of source files for secure delivery of source code

A system comprising a peripheral having a timing mechanism and a node, one of which comprises a real memory space and the other a corresponding virtual memory space, is disclosed. On receiving a timing command in the real memory space, comprising references to an event and time, an entry comprising data relative to the event and time references is created in a monitoring queue of the peripheral. A current point in time is then compared, in the peripheral, to a scheduled point in time linked to an item of data relative to a time reference stored in the monitoring queue. In response, if the current point in time is after the scheduled point in time, an item of data relative to a reference linked to the item of data relative to a time reference stored in the monitoring queue is stored in the real memory space.

Remotely located timing method and device for a processing unit in an information processing system

A computer system for managing the execution of threads including at least one central processing unit which performs interleaved execution of a plurality of threads throughout a plurality of virtual processors from said same central processing unit, and a handler for distributing the execution of the threads throughout the virtual processors. The computer system further includes means for classifying threads to be executed according to several predetermined types, and the handler for distributing the execution of threads directs each thread to be executed to a virtual processor according to the type thereof.

System and method for managing the interleaved execution of threads

A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Physical manager of synchronization barrier between multiple processes

The invention relates in particular to a computer system including peripheral devices () and at least one switch () connected to each device. A first device includes a means for initiating a control of direct access to memory areas, each one of which is associated with a separate element of the system. The switch includes a means for transmitting at least a portion of the control to each element. At least one element comprises a second device including a means for receiving at least one control of direct access to a memory area of said second device, said control being received from said first device via said switch, and a means for transmitting said received control to a component of said second device. Said system allows said first device to perform a direct data transfer to or from a memory of said first peripheral device from or to each element.

System authorizing direct data transfers between memories of several components of that system

The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means () for initiating at least one command for direct access to a region of a memory external to said first peripheral and means () for receiving at least one command for direct access to a region of a memory of said first peripheral, said command being received from said at least one second peripheral, and means () for transmitting said at least one received direct access command to a component of said first peripheral. The controller thus allows a controller of direct access to a memory of said at least one second peripheral to carry out a direct transfer of at least one data item to or from a memory of said first peripheral from or to said second peripheral.

Controller for direct access to a memory for the direct transfer of data between memories of several peripheral devices, method and computer program enabling the implementation of such a controller

Methods and devices for characterizing the interconnection efficiency of a computer network based upon a static routing scheme are disclosed. The network comprises a plurality of items of equipment. After having determined () a plurality of types of links between said items of equipment, a theoretical number of routes per link and the associated number of links are determined () for each type of at least one subset of said plurality of types of links according to the topology of said network. The determined theoretical number of routes per link and the associated number of links are then aggregated () to estimate at least one optimal routing point characterizing the theoretical efficiency of the network. Such optimal routing points can be compared with estimated actual routing points based upon the aggregation of actual numbers of routed per link and associated actual numbers of links to characterizes the network efficiency.

Growing community of inventors

Villard Bonnot, France

Philippe Couvee