Stmicroelectronics S.a.

Stmicroelectronics (rousset) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics (crolles 2) Sas

France Universite D'aix-marseille

Philippe Candelier

Richard P Fournel

Joel Damiens

Philippe Gendrier

Fabrice Marinet

Jean-Pierre Schoellkopf

Stéphane Denorme

Elise Le Roux

Laurent Dedieu

Noureddine Larhriq

Arnaud Regnier

Cyrille Dray

Francois Jacquet

Jean-Michel Mirabel

Emmanuel Josse

Jean Lasseuguette

Daniel Caspar

Romain Laffont

Thierry Devoivre

Rachid Bouchakour

Sylvie Bruyere

Pascal Masson

Virginie Bidal

Jean-Marc Tessier

Sébastien Lefebvre

Sébastien Poirier

Emmanuel Vincent

Elise Leroux

A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.

Electronic chip memory

A device includes at least three memory cells. For each cell, there is a first doped semiconductor area and a switch coupling the cell to the first area. First doped semiconductor zones connect the first areas together. A memory can include a number of the devices. For example, the cells can be arranged in a matrix, each device defining a row of the matrix.

A device includes a number of irreversibly programmable memory points. Each irreversibly programmable memory point includes a first semiconductor zone and a gate located on the first zone. A conductive area defines the gates of the memory points. First and second semiconductor areas are respectively located on either side of a vertical alignment with the conductive area. The first zones are alternately in contact with the first and second areas.

An integrated circuit includes a silicon-on-insulator substrate that includes a semiconductor film located above a buried insulating layer. A first electrode of a silicide material overlies the semiconductor film. A sidewall insulating material is disposed along sidewalls of the first electrode. A dielectric layer is located between the first electrode and the semiconductor film. A second electrode includes a silicided zone of the semiconductor film, which is located alongside the sidewall insulating material and extends at least partially under the dielectric layer and the first electrode. The first electrode, the dielectric layer and the second electrode form a capacitor that is part of a circuit of the integrated circuit.

Method for producing one-time-programmable memory cells and corresponding integrated circuit

An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an MOS capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer.

A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Method for controlling the breakdown of an antifuse memory cell

A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Secure non-volatile memory

A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.

Method for manufacturing an antifuse memory cell

A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Non-volatile reprogrammable memory

A non-volatile memory device includes a network of non-volatile memory cells, each comprising a floating-gate transistor, said network of cells being intended to store data in the form of a set of data words. The device includes a circuit which detects loss of charges stored in the cells and then reprograms the cells for which a loss of charges has been detected so as to restore the level of stored charges.

Non-volatile memory device with periodic refresh and method of programming such a device

A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer () of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.

Integrated electronic circuit incorporating a capacitor

A method is for detecting and correcting errors for a memory storing at least one code block including information data and control data. The method includes reading and decoding each element of the at least one code block to deliver an information item representative of a number of errors in the at least one code block. The method further includes, when the number of errors exceeds one, modifying a parameter of the read by a chosen value, and performing a reading and decoding of the at least one code block again to obtain a new error information item.

Growing community of inventors

Saint Mury Monteymond, France

Philippe Candelier