Micron Technology Incorporated

Innovative Silicon S.a.

Innovative Silicon Isi Sa

Philippe Bruno Bauser

David Edward Fisch

Jean-Michel Daga

Eric Carman

A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage.

Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same

A method of generating a voltage on an integrated circuit device comprising a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit device further comprises voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, (ii) apply a second voltage to a second group of associated bit lines, (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.

Techniques for controlling a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for controlling a semiconductor memory device including applying a plurality of voltage potentials to a plurality of memory cells arranged in an array of rows and columns. Applying the plurality of voltage potentials to the plurality of memory cells may include applying a first voltage potential to a first memory cell in a row of the array via a first respective bit line and a first switch transistor, applying a second voltage potential to a second memory cell in the row of the array via a second respective bit line and a second switch transistor, and applying a third voltage potential to at least one third memory cell in the row of the array via at least one third respective bit line and at least one third switch transistor, wherein the at least one third memory cell may be located between the first memory cell and the second memory cell in the row of the array.

Techniques for controlling a semiconductor memory device

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell is programmable to store one of a plurality of data states, and (ii) a bit line, having a plurality of memory cells coupled thereto. Memory cell control circuitry applies one or more read control signals to perform a read operation wherein, in response to the read control signals, a selected memory cell conducts a current which is representative of the data state stored therein. Sense amplifier circuitry senses the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the selected memory cell. Current regulation circuitry is responsively and electrically coupled to the bit line during a portion of the read operation to sink or source at least a portion of the current provided on the bit line. Sensing circuitry responsively couples the current regulation circuitry to the bit line during the portion of the read operation.

Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same

Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a memory cell array comprising a plurality of memory cells. The apparatus may also include a first data sense amplifier circuitry including an amplifier transistor having a first region coupled to at least one of the plurality of memory cells via a bit line. The apparatus may further include a data sense amplifier latch circuitry including a first input node coupled to the data sense amplifier circuitry via a second region of the amplifier transistor.

Techniques for sensing a semiconductor memory device

A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry.

There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by read circuitry to read the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.

Method and circuitry to generate a reference current for reading a memory cell, and device implementing same

There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference current which is employed by sensing circuitry to sense the data state of a memory cell during a read operation of one or more memory cells. The control, adjustment, determination and/or modification of the reference current levels may be implemented using many different, distinct and/or diverse techniques and circuitry, including both analog and digital techniques and circuitry.

Growing community of inventors

Divonne Les Bains, France

Philippe Bruno Bauser