International Business Machines Corporation

Philipp Panitz

Jens Leenstra

Markus Kaltenbach

Markus Buehler

Markus Olbrich

Juergen Koehl

Philipp Oehler

Maarten Jakob Boersma

Tim Niggemeier

Thomas Buechner

Hans Schlenker

Lei Wang

Christoph W Wandel

Markus Kaltenback

Juergen Kuehl

A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Instruction scheduling approach to improve processor performance

Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file.

Mechanism to speed-up multithreaded execution by register file write port reallocation

Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function.

Apparatus and method for calculating an SHA-2 hash function in a general purpose processor

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

Techniques for reusing components of a logical operations functional block as an error correction code correction unit

A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization engine from a design of a processor and data representing optimization goals and constraints and a code stream, wherein the processor has at least two execution pipes and at least two registers, and wherein the design comprises data for processor instruction latency and execution pipes, and wherein the code stream comprises processor instructions with corresponding register selections; and reordering means to generate an optimized code stream from the code stream with the optimal solution provided by the optimization engine for the optimization model by reordering the code stream, such that optimum values for the optimization goals under the given constraints are achieved without affecting the operation results of the code stream.

Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.

Byte selection and steering logic for combined byte shift and byte permute vector unit

Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

Calculating a timing delay in a repeater network in an electronic circuit. The repeater network comprises a plurality of driving cells. At least one loop comprising one or more pins and one or more driving cells for driving the loop is implemented. Each driving cell in the loop is arranged between two branches of the loop. For each driving cell, the loop is opened a plurality of times per driving cell, with one open at a time. A dedicated arrival time of a signal at each sink of the repeater network for the one open at a time per driving cell is calculated. The dedicated arrival time is stored. The calculation step and the storing step is repeated until the dedicated arrival time at each sink of the repeater network is available for each of the opens per driving cell.

Method and system for calculating timing delay in a repeater network in an electronic circuit

A method comprises determining gate configuration from a standard cell library for optimizing behavior of a logic gate in an electronic circuit to be resized. The determining includes defining variables for the logic gate to be resized and defining nets influenced by the logic gate to be resized. The determining includes determining constraints relative to other logic gates in the electronic circuit affected by the logic gate to be resized and formulating objective function. The determining includes solving the objective function using a linear programming solver based on the defined variables and the determined constraints. The determining includes outputting solving of the objective function obtained by linear programming solver for further processing. The gate configuration is selected from the standard cell library for optimizing behavior of the logic gate to be resized based on solving of the objective function.

Gate configuration determination and selection from standard cell library

A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound.

Estimating power consumption of an electronic circuit

A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration.

Glitch power reduction

The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

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Schoenaich, Germany

Philipp Panitz