Qorvo Us, Inc.

Rf Micro Devices, Inc.

Philip W Mason

Michael Carroll

Julio C Costa

Daniel Charles Kerr

Merrill Albert Hatcher, Jr

Christian Rye Iversen

Edward T Spears

Ali Tombak

Jan Edward Vandemeer

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m·K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

RF devices with enhanced performance and methods of forming the same

The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate

A switch branch that improves voltage uniformity across a series stack of an n-number of transistors is disclosed. A first one of the n-number of transistors is coupled to an input terminal, and an nth one of the n-number of transistors is coupled to an output terminal, where n is a positive integer greater than one. Predetermined parasitic capacitances associated with each of the n-number of transistors are adjustable with respect to capacitance value by predetermined amounts by dimensioning and arranging at least one metal layer element in proximity to the series stack of the n-number of transistors. Capacitance values for the predetermined parasitic capacitances are selected such that a voltage across the series stack of the n-number of transistors is uniformly distributed. In this way, the n-number of transistors can be reduced without risking a transistor breakdown within the series stack of the n-number of transistors.

Voltage equalization for stacked FETs in RF switches

The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.

Remote gate protection diode for field effect transistors

The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element.

Growing community of inventors

Greensboro, NC, United States of America

Philip W Mason