International Computers Limited

Philip V Rose

Colin Martin Duxbury

John Richard Eaton

Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

Pipelined data processor with parameter files for passing parameters

A pipelined data processing system comprises a series of pipeline stages through which instructions pass sequentially. If an error associated with a particular instruction (e.g. an illegal instruction) is detected, a Mayday signal is produced. This does not become active immediately. Instead it is passed down the pipeline along with the instruction that caused it, and becomes active only if that instruction attempts to terminate at the end of the pipeline. When the Mayday becomes active, it causes an interrupt to a diagnostic processor. If, on the other hand, the instruction that caused the Mayday is aborted, or does not attempt to terminate, then the Mayday is discarded and does not become active. This prevents unnecessary diagnostic actions.

Apparatus and method for detecting errors in a pipeline data processor

In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

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Philip V Rose