Newport Media, Inc.

Philip Treigherman

Chaoliang T Chen

Tracy C Denk

Nabil R Yousef

James Carwana

Jun Tang

Jun Ma

Yongru Gu

A method and apparatus for de-interleaving interleaved data in a deinterleaver memory in an Orthogonal Frequency Division Multiplexing (OFDM) based Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver. In different embodiments, the apparatus comprises of a OFDM symbol counter along with a divider or a buffer pointer RAM with circular pointer logic, a first lookup table to obtain delay buffer size and interleaving lengths for a given OFDM transmission layer, and a second lookup table to obtain buffer base address and interleaving lengths for a given OFDM transmission layer.

Area and power efficient architectures of time deinterleaver for receivers

A multi-chip antenna diversity architecture and method includes a first receiver chip that receives a first input signal from a first antenna. The first receiver chip includes a first tuner that amplifies the first input signal, a crystal operatively connected to a first crystal oscillator circuit, and a first crystal oscillator clock buffer that receives a clock signal from the first crystal oscillator circuit. A first demodulator demodulates the input signal received from the first tuner. A second receiver chip receives a second input signal from a second antenna. The second receiver chip includes a second crystal oscillator circuit, a second crystal oscillator clock buffer, a second tuner, and a second demodulator that receives diversity data from the first demodulator. The first crystal oscillator clock buffer drives the clock signal to the second crystal oscillator clock buffer, the second tuner, and the second demodulator of the second receiver chip.

Multi-chip antenna diversity picture-in-picture architecture

Area and power efficient architectures of time deinterleaver for ISDB-T receivers

A system and method for increasing the throughput of a RS decoder in MediaFLO&#x2122; receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput.

Memory architecture for high throughput RS decoding for MediaFLO receivers

A technique for segmented frame synchronization for Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) and Integrated Services Digital Broadcasting-Terrestrial Sound Broadcasting (ISDB-TSB) systems, wherein the method comprises receiving a wireless digital signal comprising an Orthogonal Frequency Division Multiplexing (OFDM) frame, further comprising ODFM symbols, in a receiver and wherein the receiver comprises a time de-interleaver, a bit de-interleaver, and a descrambler; filling memory of time de-interleaver and bit de-interleaver by the received wireless digital signal; determining an OFDM segmented frame boundary when memory of the time de-interleaver and bit de-interleaver are full; decoding bits from time de-interleaver and bit de-interleaver using a Viterbi decoder; outputting the Viterbi decoding bits from time de-interleaver and bit de-interleaver when the OFDM segmented frame boundary is detected; obtaining a segmented multiplexing frame boundary upon receipt of the first bit from the Viterbi decoder; and synchronizing the OFDM frame based on the segmented multiplexing frame boundary.

Segmented-frame synchronization for ISDB-T and ISDB-TSB receiver

Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of the interleaved data and a buffer address calculation module for generating buffer address in the buffer. The system performs memory sharing of the time and frequency de-interleaver for ISDB-T receivers and reduces the memory size required for performing de-interleaving in an ISDB-T receiver and combines the frequency and time de-interleaver buffers into one RAM thereby reducing the memory size.

Memory sharing of time and frequency de-interleaver for ISDB-T receivers

A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS demux, the RS decoder, and the system bus through time-multiplexing, wherein the RAM unit is adapted to (i) access multiple-words per clock cycle, and (ii) cache write and read accesses to reduce memory access from the TS demux and the system bus, and wherein the RAM unit is adapted to be clocked at a speed higher than an interfacing data-path to increase an effective throughput of the RAM unit. The RAM unit may comprise multiple RAM sub units, wherein while a first RAM sub unit is clock gated, the remaining multiple RAM sub units are accessible.

Integrated MPE-FEC RAM for DVB-H receivers

Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.

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Newport Beach, CA, United States of America

Philip Treigherman