International Business Machines Corporation

Philip T Wu

Yuen H Chan

Anthony Gus Aipperspach

Delbert Raymond Cecchi

William Hugh Cochran

Arthur D Tuminaro

David Peter Swart

Dale Arthur Heuer

Joseph M Fitzgerald

John Steven Mitby

Michael E Brossard

Balsha R Stanisic

Hyung S Kim

A memory sense amplifier includes a latch formed for interconnected CMOS gates with an input gate connected to one node of the latch and a reference gate connected to the other node of the latch the reference gate has an input connected to a source of reference voltage and the reference gate and input gate are activated in response to common enable signal. When the input signal, e.g., a data signal from a memory, has a signal value lower than the reference signal value when the two gates are enabled, the reference gate will discharge the node to which it is connected more rapidly than the input gate will discharge the other node. Due to the internal cross connections of the latch, the latch will rapidly change state so as to further discharge the node to which the reference is connected and further charge the other node. In this manner, a rapidly change of state of the latch is accomplished and a binary value output is generated at the latch thereby avoiding the delay which is normally encountered due to the time required for the input signal to achieve a complete change of state.

CMOS sense amplifier

A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines. The feedback circuitry uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry that discharges the voltage level of the feedback circuitry when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.

CMOS to GPI interface circuit

A combined read-only and static read/write semiconductor memory is achieved by modifying the normal threshold voltage of some of the transfer FETs in an otherwise conventional static-memory cell. A read/write data bit is recovered from an addressed cell by applying a word-line voltage higher than both the threshold voltages. Read-only data is read from the same addressed cell by using a word-line voltage higher than one of the thresholds but lower than the other, then decoding the resulting bit-line voltages. An extension allows multiple read-only bits in a single cell by lowering the cell supply voltage when read-only data are addressed.

Semiconductor static read/write memory having an additional read-only

A single-FET-per cell read/write memory having capacitor storage elements also contains a pattern of fixed, latent data represented by ion implants in some of the FETs. This pattern is loaded into the capacitors by addressing the cells with a voltage between the thresholds of the normal and the implant-modified FETs, so that some of the capacitors are discharged and others are not. Thereafter, the data may be read out, or overwritten with variable data, by addressing the cells with a voltage higher than both thresholds.

Semiconductor memory capable of both read/write and read-only operation

A memory-array sense amplifier includes a grounded-gate depletion-mode FET connected between a bit line and a sense node. Another FET connects a supply voltage VDD to the sense node when turned on by a clock phase signal. Further FETs form a latch circuit.

Sense amplifier for integrated memory array

Read-only storage chip stores three levels per single-FET cell by providing each cell with an enhancement gate, a depletion gate or no gate connection. Level decoders convert pairs of these three-level signals to triplets of two-level data signals for binary output from the ROS.

Read-only storage using enhancement-mode, depletion-mode or omitted gate

The disclosure shows a read only storage (ROS) formed of a matrix of rows and columns of field effect transistor (FET) devices which is personalized by the presence or absence of a gate at the memory device location. All circuits on the chip are controlled and restored to initial conditions by a single train of clock pulses including the row and column addresses, the array select and the output sensing. In addition the output signal is communicated directly to the output line control device without withdrawing current to set the outputs latch thereby making the output truely delayless.

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Rochester, MN, United States of America

Philip T Wu