Advanced Micro Devices Corporation

Motorola Mobility LLC

Netopia, Inc.

Philip Simmons

Denise Kerstein

Bahadir Erimli

Thomas J Runaldue

Ian S Crayford

Jayant Kadambi

Ian Lam

Jinqlih Sang

Roy Sodersjerna

Jackie Lapierre

Peter Ka-Fai Chow

Chandan Egbert

Govind Kizhepat

Eric Tsin-Ho Leung

Jack R Greasley

Richard A Relph

Robert De Mong

Various implementations disclosed herein include devices, systems, and methods for performing content generation based on audience engagement. In some implementations, a method includes presenting a first portion of content. Engagement data is obtained for an audience comprising a plurality of persons while the first portion of the content is presented. Based on the engagement data, a collective engagement level of the audience is determined for the first portion of the content. A second portion of the content that has not been presented is adjusted based on the collective engagement level of the audience for the first portion of the content in order to satisfy an engagement threshold. After adjusting the second portion of the content, the second portion of the content is presented to the audience.

Content generation based on audience engagement

A system and method for wireless DSL routing without signal interference is disclosed herein. The system includes a DSL interface, a WLAN interface, and a power system. The WLAN interface is isolated from the rest of the system by various isolation and signal interference reduction techniques. The system can be implemented in a single printed circuit board.

Wireless digital subscriber line device having reduced RF interference

A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word. A data steering means is arranged between the PCI bus and the write or read buffer to connect required pins of the PCI interface with a required location in the buffer.

Variable 16 or 32 bit PCI interface which supports steering and swapping of data

A method and apparatus for programmably driving a light-emitting diode(LED) display stores a display configuration in a register. The register contains the information identifying for which conditions in the system will status information be provided to LED drivers. When used in a system such as an Ethernet network multiport switch, for example, the status information for only those conditions and those ports identified by the display configuration stored in the configuration register will be displayed, even though status is collected for more conditions in the system.

Method and apparatus for programmably driving an LED display

A resetting, enabling and freezing system is provided for controlling a communication device in a diagnostic process. A hardware reset of the device may be performed by a host via a reset pin of a PCI interface. A software reset of the device may be provided by setting a reset bit in a command register. To stop operations of the device substantially instantaneously, a freeze mode of diagnostics is provided. The freeze mode may be initiated using hardware or software freezing. To provide the hardware freezing, diagnostic logic is supplied with a freeze signal via a freeze pin of the PCI interface. The software freezing is performed by setting a freeze bit in the command register. To enable a diagnostician to reproduce an event causing an error, an enable/disable mode of diagnostics is carried out. In this mode, elements of the device are disabled one after another in a serial fashion, with a disable signal being passed serially from one element to another. After the elements are disabled, they may be set into a chosen state to recreate a required event.

Method and apparatus for resetting, enabling and freezing a communication device in a diagnostic process

A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated on a half-duplex network port by transmitting a phantom packet to a transmitting network station if the output buffer of a destination port exceeds a programmed high threshold, or if the output buffer of the destination port exceeds a low programmed threshold and the queue of free frame pointers falls below a low programmable threshold. The switch thus provides flexibility in providing selective collisions with transmitting stations to minimize the possibility of network congestion without wasting network bandwidth with unnecessary collisions.

Method and apparatus providing programmable thresholds for half-duplex flow control in a network switch

A low-cost implementation of a switching system using a multiport network switch avoids the necessity of a microprocessor by using programmable array logic (PAL) configured to drive a non-volatile memory. The PAL includes an address generator state machine, a PCI control signal state machine, and an interrupt state machine. The non-volatile memory sequentially outputs address and data information, under the control of the address generator state machine, onto a bus connected to the network switch in order to initialize the network switch with initialization and configuration data. The PCI control signal state machine provides control signals causing the output address and data information to mimic a PCI burst transfer. Once the network switch has been configured, the non-volatile memory outputs a start command causing the network switch to begin running in a free-running mode. A memory overflow interrupt in the network switch is also enabled, causing the PAL to reset the network switch if overloaded.

Device initializing system with programmable array logic configured to cause non-volatile memory to output address and data information to the device in a prescribed sequence

A network having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on full-duplex network ports. The network switch includes a queue for storing free frame pointers that specify available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated based on the number of available frame pointers by transmitting a PAUSE frame having a selected PAUSE interval to a transmitting network station. Specifically, a full-duplex port will output a PAUSE frame having a short, medium, or long programmed pause interval if the free buffer pool of available frame pointers falls below a high, medium, or low programmable threshold, respectively. The switch thus provides flexibility in generating variable-length PAUSE control frames to minimize wasting network bandwidth.

Method and apparatus providing programmable thresholds for full-duplex

A network switch having a shared memory architecture for storing data frames includes configuration registers that are programmable by a host processor to adaptively adjust overflow buffer locations and flow control watermark levels based on monitored network traffic. The host processor allocates shared resources by setting memory configuration registers corresponding to an external memory, where the network switch uses the external memory for storing received data frames, Management Information Base (MIB) counter values, and output port overflow data. The host processor periodically reads the MIB counter values from the external memory, and adjusts flow control watermark levels or the memory configuration registers in the network switch based on rate-based network traffic derived from the MIB counter values. PCI burst transfers between the host processor and the external memory via the network switch ensure that stored data is not lost during reconfiguration of the external memory. The disclosed arrangement enables resources used by the network switch to be adjusted to minimize congestion by borrowing resources from network ports serving idle stations.

Method and apparatus for adjusting overflow buffers and flow control

Every external physical layer device coupled to a multiport data communication switch is polled in succession to determine status and control information relating to the external physical layer device. The polling procedure performed automatically at regular time intervals is interleaved with management accesses to the external PHYs initiated by a host processor. The host management access may be performed to write or read management data to or from a particular register in a particular external physical layer device.

Method and apparatus for managing external physical layer devices

An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The MIB engine decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated until the external memory is updated. The MIB engine initiates the stored MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are cleared. Reset of the MIB related storage elements in response to an external data signal is effected independently of other chip logic elements.

Growing community of inventors

San Jose, CA, United States of America

Philip Simmons