Motorola Corporation

Philip S Smith

Kuppuswamy Raghunathan

Ko-Min Chang

Michael G Gallup

Clinton C Kuo

Herchel A Vaughn

Mark S Weidner

Zener diodes that are formed concurrently with flash EEPROM cells are utilized to regulate programming voltages for programming a flash EEPROM cell (37). A selected bit-line (38) is voltage regulated with both a zener diode (19) and a bias transistor (36). The bias transistor is activated during programming to prevent breaking down a drain junction of a flash EEPROM cell, which would generate hot-electrons and cause a runaway programming problem. The regulated voltage on the bit-line is also utilized to optimize programming characteristics of a flash EEPROM cell, and to minimize disturbing a programmed logic state of flash EEPROM cells connected to a commonly selected bit-line. A separate zener diode (17) provides a regulated voltage for a selected word-line (40) during programming. By regulating the voltage of the word-line during programming, a program disturb problem associated with a high voltage word-line is minimized.

Zener regulated programming circuit for a nonvolatile memory

In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

Apparatus for reducing power consumed by a static microprocessor

A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

Cycle counter/shifter for division

A frequency generator circuit which provides an output signal which is both synchronous with and proportional in frequency to a clock signal of predetermined frequency in response to an input control signal is provided. A frequency divider portion couples a clock signal of divided frequencies to predetermined control electrodes of series-connected switches which selectively couple an output node to a reference voltage node. A decode portion selectively bypasses predetermined switches in response to the input control signal to selectively couple the reference node to the output node. A latch is coupled to the output node to hold the decoded output signal at a predetermined logic level for a predetermined amount of time.

Frequency generator circuit

A CMOS static ALU is capable of selecting one operand from a plurality of inputs and can perform various arithmetic and logic operations in addition to shift left and shift right operations. The ALU uses exclusive OR gates having a minimum number of transistors. In addition, more N-channel transistors are used than P-channel transistors which results in overall smaller size and faster operation. In addition, the ALU has a RAM cell for use as a temporary storage means which is capable of driving the ALU data bus.

CMOS Static ALU

A digital decoder for use with a dual bus system is provided having a minimum number of transistors. The decoder is easily expandable to decode larger binary coded input signals. As a minimum only six transistors are needed to decode a three-bit binary input signal to provide outputs for a data bus and its complement. By using a minimum number of transistors, less current is required for the decoder. The circuitry used to provide each decoded output is repeated in a manner which conserves silicon area when the decoder is placed on silicon. A minimum number of control lines are used.

Binary to one of N decoder having a true and a complement output

A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register. An ALU has a first and a second input, which because of the bus structure used, can both receive data simultaneously.

CMOS Microprocessor architecture

An increment/decrement circuit is provided which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/decrement circuit and also uses a reduced number of transistors. The increment/decrement circuit has a carry/borrow generator and has an increment/decrement output portion. The carry/borrow generator uses only three transistors plus an inverter and two coupling transistors. The increment/decrement output portion uses only six transistors.

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Austin, TX, United States of America

Philip S Smith