Atmel Corporation

Other

Philip S Ng

Jinshu Son

Johnny Chan

Liqi Wang

Minh V Le

Tsung-Ching Wu

Geeng-Chuan Chern

Steven J Schumann

Alan L Renninger

Tin-Wai Wong

Ken Kun Ye

Tinwai Wong

Jeff Ming-Hung Tsai

Jeffrey Ming-Hung Tsai

James C Hughes

Sai Kai Tsang

Jeffrey M Tsai

Kris Li

A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.

Memory device and systems and methods for selecting memory cells in the memory device

A slip cutch for a roller blind that includes a clutch base with a shaft portion, a drive sprocket including a drive tube and rotationally mounted on the clutch base, at least one clutch spring and a roller tube connector. The clutch spring maybe a coil spring frictionally engaged about the shaft portion and positioned between the shaft portion and the drive tube. The spring includes end members that engage the drive tube such that rotation of the drive tube about the shaft portion is resisted by the frictional engagement of the spring about the shaft. The roller tube connector is secured about the drive tube and rotates with the drive tube about the shaft portion. The roller tube connector is free from contact with the clutch spring.

Slip clutch for roller shade

Selecting memory cells using source lines

The present invention is a noise tolerant communication protocol device and method where a clock signal input, triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device, in determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol, device from measurement of the time reference pulse magnitude.

Communication protocol method and apparatus for a single wire device

Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group.

Digital architectures for serial data stream operations

The disclosed WLCSP solution overcomes the limitations of fan-out WLCSP solutions, and other conventional solutions for WLCSP for small, high volume die, by increasing the width of scribe regions between die on a semiconductor substrate to accommodate bonding structures (e.g., solder balls) that partially extend beyond peripheral edges of the die. The scribe regions can be widened in x and y directions on the wafer. The widened scribe regions can be incorporated into the design of the mask set.

Method of computing a width of a scribe region based on a bonding structure that extends into the scribe reigon in a wafer-level chip scale (WLCSP) packaging

The present invention is a noise tolerant communication protocol device and method where a clock signal input triggers an internal delay clock in an integrated circuit. Data is presented to an input pin and sampled prior to the next external clock pulse based on the internal delay clock. A data pulse value is distinguished by input signal voltage level and not by pulse length. Sampling of data bits is deferred until a signal level is most likely stable, thereby avoiding sampling during periods around edges of changing data values. Therefore, error detection and correction circuitry is not required. A time reference pulse, produced by a bus master, is measured by the protocol device to determine a data transmission rate by the master. The timing of sampling of input signaling from the master is determined by the protocol device from measurement of the time reference pulse magnitude.

A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF).

Snap-back tolerant integrated circuits

Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation circuitry includes a standby mode logic circuit responsive to a standby mode signal received at one of its inputs and provides an output signal to a gate of an active switching device located in a path between an external pin of the integrated circuit and the internal high capacitive node. The output signal keeps the active switching device turned off for the duration of the ESD test or ESD event. The standby mode logic circuit transparently passes an input logic signal to the active switching device whenever the integrated circuit is in a normal operating mode.

Capacitive node isolation for electrostatic discharge circuit

A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a second line to carry a clock signal between the devices. A pullup resistor is located in each part of the communications bus circuit; the pullup resistor in the first part couples to the first line of the communications bus and the pullup resistor in the second part couples to the second line of the communications bus. To improve data throughput and reduce noise, an active pullup device, working in conjunction with the pullup resistor, is located in each part of the communications bus circuit, providing a high logic level on at least one of the communications bus lines.

Serial communications bus with active pullup

A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Circuit to control voltage ramp rate

A single-wire interface communication system is capable of providing both electrical communication of signals and power between devices coupled to the system. Coupled to the single-wire interface is at least one target device which contains a PMOS transistor, a charge storage device, an inverter controlling the PMOS transistor, and a target device function. The charge storage device provides power to the target device function and to the inverter. The PMOS transistor receives power from the single-wire interface at a power-supply voltage level and charges the charge storage device to the same level. Non-communication periods produce a charging period sufficient for the charge storage device to attain the power-supply voltage level.

Device and method of supplying power to targets on single-wire interface

An electronic test structure and method for testing non-volatile memory cells. The structure includes a first transistor coupled in series to a floating gate transistor whereby a source of the first transistor is coupled to a positive power supply voltage and a source of the floating gate transistor is coupled to a power supply ground. A gate of the first transistor is further coupled to a source of the first transistor. A second transistor is coupled in series with a memory cell with a source of the second transistor coupled to a positive power supply voltage and a gate of the second transistor is coupled to the drain of the first transistor.

Indirect measurement of negative margin voltages in endurance testing of EEPROM cells

A method of testing power-on reset circuitry in an integrated circuit comprises establishing the a first state of the integrated circuit that is different from a normal reset state of the circuit, lowering the VCC power supply voltage from a normal high operating level Vto a specified lower level Vthen raising it back to the normal high level, then determining whether or not the integrated circuit has assumed the reset state. The testing can repeated with a plurality of lower VCC levels Vand under a variety of operating conditions to characterize resetting parameters and to designate pass/fail results for individual chips. If an AC voltage detector is part of the power-on reset circuitry, then it can tested separately, and DC testing occurs with very slow ramp rates for lowering and raising the power supply voltage.

Growing community of inventors

Cupertino, CA, United States of America

Philip S Ng