International Business Machines Corporation

Philip S Honsinger

Vinod Narayanan

Andrew D Huber

Shuhui Lin

Gustavo Enrique Tellez

Scott Whitney Gould

Andreas Huber

Juergen Koehl

Hubert Harrer

John Youssef Sayah

Dierk Kaller

Patrick M Ryan

Reginald B Wilcox, Jr

Steven G Lovejoy

Bernhard Korte

Charles L Meiley

Jens Vygen

Gary R Doyle

Gorden S Starkey

Lok T Lui

Ling-Hui Hao

Hai H Chen

Thomas J Lavery

Martin Kindscher

Lucy Lim

Lok Tin Liu

Ulrich Brenner

Andre Rohe

A technique for routing signal traces in an electronic package design includes extracting near-end and far-end crosstalk values for traces and vias from a model of the electronic package design. The extracted values are then length-normalized and the normalized values are allocated to coupling factors of a cost-function. A first bus routing for the electronic package design is performed to provide a first routed design. Length segments from the first routed design are extracted and inserted in the cost-function. Crosstalk for each bus net is accumulated using the cost-function. In response to the accumulated crosstalk being less than a determined limit, the first routed design is saved. In response to the accumulated crosstalk being greater than the determined limit, an additional bus routing for the electronic package design is performed.

Cost-function based routing techniques for reducing crosstalk in electronic package designs

A method and system for placing logic nodes based on an estimated wiring congestion are provided. Specifically, under the present invention, relative probabilities for potential implementations of wiring interconnects between logic nodes are determined. Then, for each edge between adjacent bins, a total of corresponding relative probabilities is compared to a wiring availability. Based on the comparison, the logic nodes can be placed within wiring constraints.

Method and system for placing logic nodes based on an estimated wiring congestion

Disclosed is a method of routing power from a power network to one or more power service terminals within a voltage island, comprising: dividing the power network into segments; creating power service terminal to segment connections based on a first set of criteria; removing selected power service terminal to segment connections based on a second set of criteria; and selecting one power service terminal to segment connection for each the power service terminal. The first criteria is includes power drop, wire length, wire size, wiring layer restrictions and the second criteria includes electro-migration, wire length and current criteria.

Method of wiring power service terminals to a power network in a semiconductor integrated circuit

A method for automatically wiring (i.e., routing) an integrated circuit chip after completing the placement of cells on the chip is described. The method employs a maze routing such that the spacing between the routed wires is increased, while at the same time maintaining control over the total wiring length. The maze routing herein described is modified to improve chip yield, reduce wiring capacitance, limit power consumption and coupled signal noise, all of which are achieved by increasing wire-to-wire spacings.

Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing

A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure. Further spatial restriction within one or more symbolic layers is provided by means of an applications window entity. Data compaction is provided by provision of data sharing of area spec entities by plural area entities which are otherwise uniquely maintained.

Hierarchical data model for design automation

A method for assigning interconnection resources to input/output connection points on differential current switch logic elements which need to use the resources, but which introduce an order dependency to the assignment problem, due to restrictions unique to differential current logic. The input/output connection points are paired first as are the interconnection resources. Pairing removes the order dependency. An assignment is then made through the use of an optimizing linear assignment algorithm suitable for single input/output connection point to single interconnection resource assignments. Preferably, a cost matrix is generated to determine the optimum assignment by minimizing the total assignment cost. The paired assignments are then broken apart to assign each individual member of the point pair to an individual member of the assigned resource pair. The final assignment of the individual pair members is compared to legality constraints, the violation of which may have been masked in the calculation of assignment costs of the pairs.

Interconnection resource assignment method for differential current

A routing method for differential current switch (DCS) pairs initially shortens the min/max length window for a first routed rail in order to increase the likelihood that length of the second rail will fall within the window. Next, the routing domain for the first rail is modified so that the first pin exit direction to the route is toward the second pin of the differential current switch pair. A suitable algorithm, such as a prior art mazerouter algorithm, is used to route the first rail along a path restricted to the routing domain. At each proposed via connection for connecting the first rail route from one plane to another, the program accepts the proposed via connection only if there is an available adjacent via for routing the second via. If a via for routing the second rail is not available, the proposed route for the first rail is rejected.

Automatic DCS routing for multilayer packages to minimize coupled noise

A wiring methodology for optimizing the wiring of multiple wiring media packages. Data models are created for the package and for the networks which embody the circuit design logic of the package. These data models represent the design data and the contrasting electrical and geometrical characteristics of the different media in a form suitable for the operation of wiring algorithms. In the preferred embodiment, one or more constraint models are associated with each wiring network. The electrical properties and availability limits of all wiring resources are included in the data model. The data model is then used in the selection of a rough path for each connection and the assignment of networks and portions of networks to particular media. The rough path serves as a basis for estimates of the characteristics of the wiring solution for each network. Network assignments and estimates are made globally, considering the information for other networks and package design constraints incorporated into the data model. After assignment of media, networks are partitioned into subconnections. Interface via selection is optimized through a process whereby each possible combination between network pins needing vias and available vias is evaluated with respect to a set of costs. Estimates made in prior steps are used to generate these costs. Following via selection, detail routing can then be implemented by segmenting the wiring problem into separate problems for each medium. These separate problems can be resolved sequentially in no particular order.

Method to optimize the wiring of multiple wiring media packages

A method of assigning pins to corresponding connection points in the design of computer modules where connection points on one layer need to be electrically connected through the pins to a wiring layer so as to minimize the length of the wiring between the points. A best area for selecting a pin is identified for each point that needs to use a pin, and pins are preferentially assigned to the points from their respective best areas. The method introduces a consideration of the direction of the destination point into the assignment solution and allows previous assignment methods to be used which incorrectly assumed that the direction to the destination point could be ignored.

Method for assigning pins to connection points

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Poughkeepsie, NY, United States of America

Philip S Honsinger