Tektronix, Inc.

Other

Null Networks LLC

Textronix, Inc.

Flashtiming LLC

Philip S Crosby

Charles H Van Dusen

Yih-Chyun Jenq

Alejandro E Icaza

Bruce J Penney

Eric Carlson

J Lynn Saunders

Allen L Hollister

Ajay K Luthra

James L Gimlett

Larry A Nelson

T Naveen

Clifford H Moulton

Dale A Jordan

Charles Wesley Rhodes

Venkataraman Prasannan

Sarah J Marlino

Ali Tabatahai

Improved systems and methods for timing athletic events. A radio-based starter unit and a radio based timer unit communicate wirelessly via radio. Push buttons/switches and lights and a speaker in the units provide an intuitive, easy to use interface. Handshaking occurs between the starter unit and the timer unit, and lights indicate that the event is ready to start. Real time clocks in the units are synchronized. Upon detection of race or other event start, such as from a starter's pistol, information indicative of the race start time is transmitted from the start unit to the timer unit. A camera in communication with the timer unit provides video frames, and the timer unit encodes and inserts elapsed time information in the video frames, which are then output from the timer unit for review and analysis on a computer.

Systems and methods for timing athletic events

Methods and apparatus are provided in accordance with the present invention in which a control mechanism, such as for example, a microcontroller, provides an interface between an optical transponder and an external control system, such that monitoring and controlling of the optical components of the optical transponder are accomplished in an efficient and cost-effective manner. In some embodiments of the present invention, methods and apparatus provide for testing and calibration of the optical transponder without removing any portion of a protective housing within which the internal components of the optical transponder are disposed.

Method of making an optical transponder

Optical transponder

An apparatus and method for measuring delay variation of a regenerated data clock and of the associated data packet has a first-in/first-out (FIFO) buffer to which an input clock associated with the data packet and data from the data packet are input. A sample clock derived from a regenerated data clock is used to clock the data out of the FIFO buffer, the regenerated data clock being a function of a reference frequency signal and a period control parameter. The regenerated data clock and input clock are compared to determine a buffer occupancy for the FIFO buffer, from which the period control parameter is derived. From the period control parameter and the buffer occupancy delay variation of the regenerated data clock and of the associated data packet is calculated.

Measuring delay variation of regenerated data clock and of associated data packets

An apparatus for video clock and framing signal extraction by transport stream snooping parses MPEG2 Transport Packet headers from a transmission transport stream and partially decodes the headers to identify those corresponding to a specified packet identification (PID). From the specified headers a program clock is decoded and compared with a recovered program clock generated by a local clock oscillator and a local clock counter. The comparison is used to finely tune the recovered program clock frequency. Also from the heads video framing information is decoded, and such framing information and the recovered program clock are used to generate a video reference signal.

Video clock and framing signal extraction by transport stream &ldquo;snooping&rdquo;

A switcher using shared processors has an input matrix with a plurality of inputs to which a corresponding plurality of sources may be coupled. One or more of the sources may provide compressed data. The input matrix routes selected ones of the sources to a plurality of outputs which is less in number than the number of inputs, the routing being determined by a tally output. A pool of processors, such as compression decoders, color correctors or the like, are coupled to the outputs of the input matrix as needed for processing those sources that require such processing to provide processed data. The outputs of the processors provide processed data to a conventional switcher that combines the selected processed data to provide a program output. The conventional switcher also provides the tally output. For sources that provide inter-frame compressed data, the conventional switcher provides a preview output and a preview tally output so that the necessary time delay for decompressing such data is anticipated to minimize delay in switching the preview output to the program output. A resource management module keeps track of which processors are committed to which sources.

Switcher using shared decompression processors for processing both

An enhanced video data compressor has a composite video signal decoder that changes the state of a field identification signal in response to a vertical interval indicator in composite video data which is in a digital video format. Thereafter a vertical timing pulse is generated to prepare a compression encoder to acquire data. By counting lines from the vertical timing pulse the decoder sets a horizontal timing signal at a one macroblock line interval prior to active video data so that the compression encoder acquires video data from the vertical interval as well as active video data. At the end of each field the acquired data is processed by the compression encoder to produce compressed video data.

Video compression enhancement

A video quality improvement method and apparatus for a television system recovers lost brightness information from the chrominance channels of an encoder due to processing errors, such as quantization roundoff errors, and adds it to the luminance input to the luminance channel of the encoder. Component signals from a video source are input to the encoder. The encoder provides an encoded video output signal as well as reconstructed component signals. From the encoder characteristics the processing errors for the chrominance channels are determined. The partial derivatives for each of the component signals are obtained, and the error in brightness is determined by summing the products of the errors and the corresponding chrominance partial derivatives. The luminance component signal is corrected by dividing the error in brightness by the luminance partial derivative and subtracting the result from the input luminance component signal. The corrected luminance component signal is processed by the encoder.

Video quality improvement

An analog-to-digital converter latching circuit functions alternatively in a degenerative mode and a regenerative mode. During degeneration, circuit stray capacitances are substantially discharged for resulting in fast operation. When the circuit switches from degeneration to regeneration, a small signal current is able to start the latch in the proper direction without first having to overcome charge stored in the stray capacitances.

Analog-to-digital converter latch circuit

A format converter for converting an input signal having a specified format to a digital signal of a pre-existing format, and for converting the digital signal back to the input signal automatically, loads an active data portion of the input signal into an input first-in/first-out (FIFO) buffer at a first data rate and reads the active data portion together with dummy filler samples from the FIFO at a second data rate as the digital signal. The number, location and/or values of the filler samples identify the specified format. In reverse the filler samples are stripped from the digital signal and the resulting active samples are loaded into an output FIFO at the second data rate. The stripped filler samples are used to determine the specified format of the original source of the data signal, and the active samples are read from the output FIFO at the first data rate in the specified format to reproduce the input signal.

Format converter architecture

A sampling phase detector for a phase locked loop system receives a gate signal derived from the output of a voltage controlled oscillator to enable the phase detector. A reference signal is applied to the phase detector to charge one of two capacitors during the gate period, the capacitor being charged being determined by the state of the reference signal. At the end of the gate period the difference in charge between the two capacitors is transferred to the output of the phase detector as a control voltage signal to correct the output of the voltage controlled oscillator to be in phase wiht the reference signal.

Phase detector

An analog-to-digital converter comparator circuit includes a pair of differential amplifiers having their outputs normally intercoupled in a subtractive sense. At a sampling strobe time, the output of one differential amplifier is reversed such that outputs of the two differential amplifiers are additive. The period of time during which the output signals add can be made as short as desired, for example by successively operating differential coupling circuits at the amplifier outputs through an intervening delay line. A very small aperture time is secured which is substantially shorter than the time constant of subsequent circuitry. A latch circuit receives the output of the comparator for assuming one of two different states in accordance with the comparator sampled output.

Analog-to-digital converter comparator circuit utilizing a reverse

An apparatus for counting the number of times that each of a large number of digital data patterns are present on a set of signal lines comprises a plurality of random access memories (RAMs) and a feedback means, arranged to form an array of linear feedback shift registers. The data to be analyzed is applied to the address inputs of the RAMs where it selects one of the linear feedback shift registers in the array. A data-valid signal associated with this data causes the selected linear feedback shift register to increment (or decrement) in its pseudo-random count. After the analysis period is over, the value at each address is read out and translated using a lookup table or other translating means from the pseudo-random code of the linear feedback shift register into a meaningful number. This result may then be displayed; for example, in a histogram. An improved feedback path for the linear feedback shift register avoids hang-up states and the need for initialization. A mux can be used to switch between two alternative feedback paths, allowing the apparatus to operate in a count-up mode or a count-down mode.

Data occurrence frequency analyzer

A sampling streak oscilloscope responsive to a light input signal stores charges on a CCD target by means of an electron beam rapidly scanned across a narrow dimension of the CCD target in coincidence with a segment or portion of the light input signal. The time relationship between a streak and the light input signal is changed to record a charge pattern for another segment of the input signal, while charges representative of a prior segment are transferred along the CCD array. A representation of the entire input signal is built up in memory.

Light signal sampling system

A circular scan streak tube system for recording fast optical data includes a target having a first array of detection elements and a second array of corresponding storage elements. Changes in the scanning electron beam current representing optical events are detected and stored in the first array. The first and second arrays are segmented into two halves for continuous operation. Data stored in one half of the first array are transferred into the corresponding storage elements while data are written into the other half of the first array. Data stored in the first array are transferred in parallel to the second array. After a triggering event, the data are shifted circumferentially through the second array for output as serial data. The target is formed in a unitary planar semiconductor substrate having a buried channel for storing and conducting electric charge representing the stored data.

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Portland, OR, United States of America

Philip S Crosby