Nxp B.v.

Koninklijke Philips Corporation N.V.

Nexperia B.v.

Philip Rutter

Steven Thomas Peake

Nicolas J Wheeler

Jan Sonsky

Raymond J Grover

Matthias Rose

Leonardus A De Groot

Christopher Martin Rogers

Georgios Petkos

Henricus Cornelis Johannes Buthker

Maarten Jacobus Swanenberg

Jan Dikken

Barry Wynne

Yan Lai

Miron Drobnis

Andrew Butler

Chris Rogers

Kuldeep Kanwar

A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

Semiconductor device and a method of making a semiconductor device

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

Circuitry with voltage limiting and capactive enhancement

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Trench-gate RESURF semiconductor device and manufacturing method

Embodiments relate to a diode circuit which uses a Schottky diode. A parallel bypass branch has a switch and bypass diode in series. The operation of the switch is dependent on the voltage across the Schottky diode so that the bypass function is only effective when a desired voltage is reached. The diode circuit can be used as a replacement for a single diode, and provides bypass current protection preferably without requiring any external control input.

Diode circuit and power factor correction boost converter using the same

A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.

Cascoded semiconductor devices

A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.

Cascode semiconductor device for power factor correction

A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.

Cascode circuit

A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.

Vertical MOSFET transistor with a vertical capacitor region

A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.

Semiconductor device with gate trench

An isolation region () is formed between an edge termination region () having deep trenches () and the central region (). The isolation region includes gate fingers () extending from the edge gate trench regions () to the gate trenches () in the central region () to electrically connect the edge gate trench regions to the gate trenches () in the central region. The isolation region also includes isolation fingers () extending from the edge termination region () towards the central region () and gate between the gate fingers () for reducing the breakdown voltage with a RESURF effect.

Edge termination region of a semiconductor device

A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region () of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Trench gate MOSFET and method of manufacturing the same

A dc-to-dc converter has two field effect transistors connected in series between an input terminal and a ground terminal. Adjustment of the dead time when both transistors are off is carried out by providing Kelvin feedback connections directly across the drain and source of one or both of the transistors, so bypassing signal line resistance and inductances.

Dead time control in a switching circuit

Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

Trench-gate semiconductor device and method of manufacturing

A driver circuit includes monitoring circuitry () for monitoring the states of high and low side switches (). The driver circuit has an adjustable delay for turning on the transistors (). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage Vbefore a voltage corresponding to the other transistor passes another predetermined point Vand vice versa.

Driver for switching circuit and drive method

A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (), for example of polysilicon gate material, extends on an intermediate insulating layer () over a higher-doped (P+) end region () of the channel-accommodating region (). This insulating layer () comprises an area () of a trench-etch mask (), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (). A window () extends through the trench-etch mask () at a location where an end trench () extends into the P+ region (). The end trench () is an extension of the insulated gate trench () into the P+ region () and accommodates an extension () of the trench-gate (). The conductive layer () is connected to the trench-gate extension () via the window (). The lateral extent of the conductive layer () terminates in an edge () that is defined on the trench-etch mask ().

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Stockport, United Kingdom

Philip Rutter