Toshiba Memory Corporation

Kioxia Corporation

Plx Technology, Inc.

Toshiba Corporation

Philip Rose

Benjamin James Kerr

Shigehiro Asano

Julien Margetts

Robert Reed

Gary James Calder

Neil Buxton

Senthil Thangaraj

Girish Desai

Saswati Das

Barada Mishra

Julien Magretts

Matthew Stephens

A system for serial communication includes a controller, a semiconductor package comprising a plurality of semiconductor die, and a serial interface configured to connect the plurality of semiconductor die to the controller. The serial interface includes a controller-to-package connection and a package-to-controller connection, and the serial interface is configured to employ a signaling protocol using differential data signaling with no separate clock signals.

Serial interface for semiconductor package

Memory systems and methods of operating the memory systems are disclose. In one arrangement, a device includes a memory device configured to store first data, a first input/output (I/O) pin, and a serial communication device configured to receive the first data and output the first data. The serial communication device is connected to the first I/O pin via a first device. The device also includes a virtual communication logic configured to receive the first data and output the first data to a communication interface connected to a host device.

System and method for in situ debug

A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.

Namespace re-sizing

A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.

System and method for serial interface memory using switched architecture

In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.

Enhanced trim command support for solid state drives

In one embodiment, a solid state storage drive comprises a plurality of flash memory devices configured to store a plurality of data clusters having a predefined data cluster size, and configured to store a first part of a first data cluster of the plurality of data clusters on a first page of flash memory and a second part of the first data cluster on a second page of flash memory, a partial buffer completion bitmap stored in a memory, wherein each bit in the partial buffer completion bitmap corresponds to a location in a buffer configured to receive data clusters read from the plurality of flash memory devices, and a controller configured to cause a page of data to be read from one of the plurality of flash memory devices, the page of data including either the first part of the first data cluster or the second part of the first data cluster, the controller including a queue buffer manager configured to change the status of a bit in the partial buffer completion bitmap when either the first part of the first data cluster or the second part of the first data cluster has been read from either the first page or the second page of flash memory and stored in the buffer. In one embodiment, the plurality of flash memory devices is further configured to store a first part of a second data cluster on the second page of flash memory and a second part of the second data cluster on a third page of flash memory.

Split-page queue buffer management for solid state storage drives

Methods and SATA devices having more than one operating state suitable for providing efficient command and data transfers over a SATA bus. A SATA device is provided for communicating with a host. The host sends commands to the SATA device and the SATA device sends data to the host in response to the commands being received by the SATA device. The SATA device has a queue of commands received from the host. The SATA device is configured to operate in a first operating state wherein the commands are received by the SATA device and the data are not sent to the host, and a second operating state wherein the commands are received by the SATA device and the data are sent to the host wherein data being sent to the host has priority over receiving commands by the SATA device.

Multi-operating state serial ATA devices and methods of operation therefor

A solid state drive (SSD) storage system includes a memory controller, host interface, memory channels and solid state memories as storage elements. The completion status of sub-commands of individual read commands is monitored and used to determine an optimal selection for returning data for individual read commands. The completion of a read command may be dependent on the completion of multiple individual memory accesses at various times. The queueing of multiple read commands which may proceed in parallel or out of order causes interleaving of multiple memory accesses from different commands to individual memories. A system and method is disclosed which enables the selection, firstly of completed read commands, independent of the order they were queued and, secondly, of partially completed read commands which are most likely to complete with the least interruption or delay, for data transfer, which in turn improves the efficiency of the data transfer interface.

System and method for efficient processing of queued read commands in a memory system

A link layer of a serial protocol is modified to perform early primitive detection. An early primitive detector unit compares an undecoded bit sequence to that corresponding to a particular primitive. A primitive notification is generated in response to identifying a match. Latency is reduced compared with performing link layer decoding and then identifying primitives.

System and method for improving the efficiency of a serial interface protocol

Mass storage devices and methods of operating thereof adapted for use with a host and for storing data thereof includes at least one non-volatile memory for storing the data, at least one volatile memory, a memory controller configured for reading and writing the data and metadata to and from the non-volatile memory and the volatile memory, and an auxiliary power supply, wherein the memory controller locates the data on the non-volatile memory with the metadata. When processing a write command that requires all data to be written to the non-volatile memory before confirmation is returned to the host computer system that the write command has succeeded, the mass storage device is configured to write the data to the non-volatile memory, write the metadata to the volatile memory, and once the both data and metadata are written, return a completion status of the write command to the host computer system.

Solid-state mass storage device and method for processing forced unit access write commands

A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full.

Single pipe non-blocking architecture

In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding commands in the plurality of system clock-controlled components; and adjusting the system clock to a slow speed based on the determination that there are no outstanding commands in the plurality of system clock-controlled components.

Growing community of inventors

Islip, United Kingdom

Philip Rose