Cisco Technology, Inc.

Tandem Computers Incorporated

Other

Nvidia Corporation

Silicon Graphics, Incorporated

Philip R Manela

Robert W Horst

Luca Cafiero

Satyanarayana Nishtala

Robert L Jardine

Mario Mazzola

Shannon J Lynch

Amit D Sanghani

Brian D Hutsell

Eduardo Marcelo Lipiansky

Eugene Feinberg

Sameer M Gauria

Daniel R Ullum

Walter E Gibson

John A Robinson

John C Lin

Peter R Birch

Ko Yamamoto

Michael A Plum

Javad Khakbaz

Jeffery A Sprouse

Jay Evan Scott Peterson

Richard F Paul

This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.

System and methods for memory expansion

In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.

Memory expansion using rank aggregation

This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.

On the fly tuning of parameters used in an interface between a memory (e.g. high speed memory such as DRAM) and a processor requesting access to the memory. In an operational mode, a memory controller couples the processor to the memory. The memory controller can also inhibit the operational mode to initiate a training mode. In the training mode, the memory controller tunes one or more parameters (voltage references, timing skews, etc.) used in an upcoming operational mode. The access to the memory may be from an isochronous process running on a graphics processor. The memory controller determines whether the isochronous process may be inhibited before entering the training mode. If memory buffers for the isochronous process are such that the training mode will not impact the isochronous process, then the memory controller can enter the training mode to tune the interface parameters without negatively impacting the process.

Tuning DRAM I/O parameters on the fly

Embodiments for generating a higher frequency test clock signal for a semiconductor device are disclosed. In an example embodiment, a clock generator may be coupled to a clock input. A test clock generator may receive a clock signal generated by the clock generator, and the test clock generator may output a higher frequency test clock signal derived at least in part from the clock signal generated by the clock generator. The test clock generator may output the higher frequency test clock signal for a configurable number of clock periods.

Test clock generation for higher-speed testing of a semiconductor device

A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.

Self-adjusting programmable on-chip clock aligner

Logic circuitry in the form of an integrated circuit includes a number of scannable registers located at various locations of the logic circuitry to continuously sample signal states thereat. In response to signalling from a maintenance diagnostic processor the scannable registers can be commanded to freeze their content for extraction and observation to determining the operating condition of the logic circuitry.

Real time observation serial scan test architecture

A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Computer architecture capable of concurrent issuance and execution of

A method of gaining access to multiple signals internal to a semiconductor chip while minimizing the number of pins dedicated for diagnostic and testing purposes. A chip designer determines which internal signals would most likely be helpful in troubleshooting and debugging a new chip design. These signals are input to a selector. A configuration register is loaded with information specifying which ones of these signals is to be routed to the output pin(s) so that they can be monitored externally by a logic analyzer in real-time. The selector only routes the currently designated signals to the appropriate output pin(s). Subsequently, a different set of signals can be selectively routed to the output pin(s) in place of the originally chosen signals.

Output pin for selectively outputting one of a plurality of signals

A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

Paired instruction processor precise exception handling mechanism

A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

Growing community of inventors

San Mateo, CA, United States of America

Philip R Manela