Intel Corporation

Tektronix, Inc.

Philip R Lantz

Sanjay Kumar

Rajesh M Sankaran

Utkarsh Y Kakaiya

Kun Tian

Parthasarathy Sarangam

Manasi Deval

Gilbert A Neiger

Ashok Raj

Narayan Ranganathan

Vedvyas Shanbhogue

Michael A Goldsmith

David J Cowperthwaite

Anjali Singhai Jain

Jason W Brandt

David A Koufaty

Gunner D Danneels

Abdul Rahman Ismail

Altug Koker

Karthik Kumar

Andrew V Anderson

Thomas Willhalm

Aditya Navale

James B Crossland

Yi Liu

Asit K Mallick

Zeshan A Chishti

Saurabh Gayen

Kiran S Panesar

Nrupal R Jani

Kiran A Patil

Mitu Aggarwal

Dhananjay A Joshi

Neerav Parikh

Vishakha Gupta

Luis Carlos Maria Remis

Christina R Strong

Alexander H Duyck

Nikhil P Rao

Rajesh Sankaran Madukkarumukumana

Rupin H Vakharwala

Alain Kagi

Pratik M Marolia

David B Johnson

Subramanya R Dulloor

Michael O Maloney

Terry Downs

Robert A Marshall

Geoffrey W Peters

Dennis D Everson

Gregory Gates

Russell Downing

Cory W Cox

Kirill Instrumentov

Stanley R Koslowski

David Jiang

Koen Koning

Sanjay K Kumar

Asaf Rubinstein

Eran Shifer

Eshel Serlin

Zvika Greenfield

Robert J Royer

Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an Inter-Domain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

Scalable access control checking for cross-address-space data movement

Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators

Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.

Technologies for offload device fetching of address translations

Embodiments of apparatuses, methods, and systems for unified address translation for virtualization of input/output devices are described. In an embodiment, an apparatus includes first circuitry to use at least an identifier of a device to locate a context entry and second circuitry to use at least a process address space identifier (PASID) to locate a PASID-entry. The context entry is to include at least one of a page-table pointer to a page-table translation structure and a PASID. The PASID-entry is to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure. The PASID is to be supplied by the device. At least one of the apparatus, the context entry, and the PASID entry is to include one or more control fields to indicate whether the first-level page-table pointer or the second-level page-table pointer is to be used.

Unified address translation for virtualization of input/output devices

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

High-performance input-output devices supporting scalable virtualization

Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

Virtual device composition in a scalable input/output (I/O) virtualization (S-IOV) architecture

Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

Highly scalable accelerator

In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.

System, apparatus and method for accessing multiple address spaces via a data mover

Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

Techniques for virtual machine transfer and resource management

In one embodiment, a processor comprises: a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and an execution circuit coupled to the first configuration register, where the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes. Other embodiments are described and claimed.

System, apparatus and method for enabling fine-grain quality of service or rate control for work submissions

Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

Scalable interrupt virtualization for input/output devices

In one embodiment, an apparatus comprises a storage device and a processor. The storage device stores a feature vector index, wherein the feature vector index comprises a sparse-array data structure representing a feature space for a set of labeled feature vectors, wherein the set of labeled feature vectors are assigned to a plurality of classes. The processor is to: receive a query corresponding to a target feature vector; access, via the storage device, a first portion of the feature vector index, wherein the first portion of the feature vector index comprises a subset of labeled feature vectors that correspond to a same portion of the feature space as the target feature vector; determine the corresponding class of the target feature vector based on the subset of labeled feature vectors; and provide a response to the query based on the corresponding class.

Efficient storage and searching of vector datasets

Managing connected data, such as a graph data store, includes a computing device with persistent memory and volatile memory. The computing device stores a graph data store with a plurality of nodes and edges in persistent memory. Each of the edges defines the relationship between at least two of the nodes. The nodes and edges may contain tags and properties containing additional information. In response to a search request query, the computing device generates an iterator object stored in volatile memory with a reference to one or more nodes and/or edges in the graph data store. The split between volatile and persistent memory allocation could be used for other objects, such as allocators and transactions. Other embodiments are described and claimed.

Technologies for managing connected data on persistent memory-based systems

Growing community of inventors

Cornelius, OR, United States of America

Philip R Lantz