Oracle International Corporation

Philip P Kwan

Dawei Huang

Zuxu Qin

Ben Chen

Long Kong

Baoqing Huang

Dabin Zhang

Maoqing Yao

Kuai Yin

A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

Method and apparatus for clock signal distribution

Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

Full-rate transmitter

Embodiments include systems and methods for calibrating clocking circuits for improved jitter performance. Embodiments operate in context of a clocking circuit coupled with a transceiver system that has a receiver that tracks a recovered clock phase according to a tracking code. For example, candidate configurations can be identified, each corresponding to a different respective combination of parameter values for programmable clocking circuit parameters. For each candidate configuration, embodiments can configure the clocking system accordingly, and can sample the tracking code over a sample window to measure a tracking code spread for the candidate configuration. The clocking circuit can be programmed according to which of the candidate configurations manifested a minimum tracking code spread, thereby effectively configuring the clocking circuit for minimum jitter generation and optimizing jitter performance of the transceiver.

Clock circuit jitter calibration

Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a '1' sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.

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San Francisco, CA, United States of America

Philip P Kwan