Analog Devices Global

Analog Devices,inc.

Philip P E Quinlan

Kenneth J Mulvaney

Shane O'Mahony

Muhammad Kalimuddin Khan

Lance Robert Doherty

Tze Lei Poo

Paul Martin Lambkin

Tao Yu

Sudarshan Onkar

A wireless sensor node is described. The wireless sensor node may include a wake-up circuitry configured to awaken the sensor when a request is received. The sensor may be placed in a sleep mode, thus saving battery usage until a wake-up signal requesting use of the sensor is received. Powering of the wake-up circuitry may be supplied through energy captured using an energy harvester. In one example, the energy for powering the wake-up circuitry is extracted from the same signal used for awakening the sensor. The wireless sensor mode may operate in a passive mode, in which the energy for powering the wake-up circuitry is harvested, or in a power supply-assisted mode, in which some of the power is provided by a power supply. High quality factors filters may be used to increase the signal-to-noise ratio of the wake-up signals, thus improving the node's ability to recognize activation requests.

Wake-up wireless sensor nodes

Systems and methods permit automatic joining of a network associated with a specified area within which wireless nodes reside. Network managers located in or near the specified area use wireless proximity detection to estimate distances to wireless nodes requesting to join the network. The network managers can use the estimated distances to determine whether or not a requesting wireless node is located within the specified area. If the requesting wireless node is located within the specified area, the network managers can permit the wireless node to join the wireless network associated with the respective specified area.

Wireless node location identification

An apparatus comprising: a signal detection circuit determine a count reached by a counter between successive detected edge signals and to provide an indication of whether successive detected edge signals are separated from each other by at least a prescribed time interval; a clock circuit that produces clock signal pulses in response to a provided indication of an occurrence of a succession of detected edge signals each separated from a previous edge signal of the succession by at least the prescribed time interval; phase matching circuitry configured to align the produced clock signal pulses with detected edge signals; and a pattern matching circuit that that samples a sequence of detected edge signals aligned with the produced clock signal pulses to detect a data packet.

System and method for reducing false preamble detection in a communication receiver

Embodiments of the present disclosure provide a digital filter module for use in receivers, particularly suitable for use in a narrow-band electromagnetic receiver. Design of the module is based on a recognition that providing to the module samples of a signal received by a receiver and sampled at a sampling frequency equal to four times the intermediate frequency of the receiver, eliminating zeros in the filter, and implementing the filter module as a resource-shared second-order filter structure that includes two sections advantageously enables saving some hardware components, particularly some multipliers and adders, in implementing a versatile digital filter module that can function either as two real filters or one complex filter. In this manner, substantial reduction of area and power consumption of the filter module may be achieved, while maintaining sufficiently high filtering performance.

Growing community of inventors

Glounthaune, Ireland

Philip P E Quinlan