International Business Machines Corporation

Philip Neil Strenski

Philip Jacob

Charles Ray Johns

David James Hathaway

Chandramouli Visweswariah

Mark Alan Lavin

Xiaoliang Bai

Lars Schneidenbach

A system and method for notifying a process about a creation or removal event of a named data element (NDE) in a coordination namespace distributed memory system. A controller runs methods to: generate a tuple corresponding to data generated by a requesting process, the tuple having a tuple name and data value; and generate a notification indicator in a pending notification list to indicate to one or more processes a notification of the creation or removal event associated with the corresponding tuple. Upon detecting the event performed on the tuple by a second process, the method further searches for NDEs in the distributed memory system having the same tuple name, and in response to determining an existence of an associated pending notification record in a pending notification list of records, notify each corresponding process of the one or more processes indicated in the list of the creation or removal event.

Tuple checkout with notify in coordination namespace system

A system and method for federating a tuple storage database across multiple coordinated namespace (CNS) extended memory storage systems allowing the sharing of tuples and tuple data across independent systems. The method provides a federation service for multiple coordination namespace systems. The method retrieves a tuple from connected independent CNS systems wherein a local CNS Controller sends a read request to the local gatekeeper to retrieve a first tuple and creates a local pending remote record. The local gatekeeper at a requesting node sends a broadcast query to a plurality of remote gatekeepers for the tuple and Remote gatekeepers at remote nodes query in its local CNS for the tuple. The Local gatekeeper process at the requesting node receives results from a plurality of remote gatekeepers for the said tuple and selects one remote gatekeeper to receive the requested tuple and broadcasts a read for tuple data with selected gatekeeper.

Sharing tuples across independent coordination namespace systems

A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k, to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.

Synchronization between processes in a coordination namespace

A system and method for supporting tuple record interlinking in one or more tuple space/coordinated namespace (CNS) extended memory storage systems. A system-wide CNS provides for efficient storing and communicating of data generated by local processes running at the nodes, and coordinated to generate a union/intersection of multiple CNS where tuple records are interlinked in multiple CNS hashtables, and/or share tuple data between two sets of processes that are part of different CNSs. Local node processes further generate multi-key tuples where two or more tuple records are interlinked within the same CNS hash table, thereby permitting a look up of the tuple data by either tuple name/keys. A CNS controller further provides a tuple iterator for a key-value storage in a CNS system that adds more links between tuples enables creation of iterator structures such as linked list or trees etc. of 'different' tuples in a tuple database.

Interlinked tuples in coordination namespace

A system and method for supporting data MapReduce operations in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing and communicating data generated by local processes running at the nodes, and coordinated to provide MapReduce operations in a multi-nodal system. A hardware accelerated mechanism supports map reduce sorting/shuffle operations and reduce operations according to an aggregate function. Local processes running at a node generate a tuple corresponding to data generated by a process, each tuple having a tuple name and tuple data value corresponding to the generated data. Each tuple is processed and stored at the node or another node, dependent upon its tuple name. Tuple records associated with a tuple name are accumulated at one or more nodes according to a linked list structure at each that is accessible via a hash table index pointer at the node.

Map reduce using coordination namespace hardware acceleration

Scatter gather operation(s) are performed by accessing a shared memory that is shared amongst nodes interconnected through network(s) and having a CNS shared amongst the nodes. Data is gathered from multiple processes at corresponding multiple nodes into location(s) in the CNS, and tuple(s) having a same tuple name are created in the CNS. The tuple(s) have information referencing the gathered data in the location(s). Alternatively, data that has been gathered using the same tuple name is scattered to multiple processes participating in the CNS. The scattering uses the tuple(s) in the CNS, and is performed from the location(s) into other location(s) at one or multiple nodes for one or multiple processes at the corresponding one or multiple nodes. Both the gathering data and the scattering data may also be performed.

Scatter gather using key-value store

A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.

A system and method of buffered freepointer management to handle burst traffic to fixed size structures in an external memory system. A circular queue stores implicitly linked free memory locations, along with an explicitly linked list in memory. The queue is updated at the head with newly released locations, and new locations from memory are added at the tail. When a freed location in the queue is reused, external memory need not be updated. When the queue is full, the system attempts to release some of the freepointers such as by dropping them if they are already linked, updating the linked list in memory only if those dropped are not already linked. Latency can be further reduced by loading new locations from memory when the queue is nearly empty, rather than waiting for empty condition, and by writing unlinked locations to memory when the queue is nearly full.

Buffered freepointer management memory system

A method for using layout enumeration to facilitate integrated circuit development includes defining an initial set of design ground rules represented in a notation compatible with a coarse placement grid, for a given layer(s) of an integrated circuit device; defining an initial region of interest for the integrated circuit device; enumerating, according to the initial set of design ground rules, each legal design layout for a given layer of the integrated circuit device in the initial region of interest; running a manufacturing simulation of the enumerated legal design layout data and, responsive to determining one or more failing layouts resulting therefrom, further determining whether the failing layouts may be eliminated by changes in technology parameters and/or updated ground rules. Upon eliminating the one or more failing layouts for the initial region of interest, expanding the initial region of interest and repeating the enumerating, manufacturing simulation, and triage assessment.

Using layout enumeration to facilitate integrated circuit development

A method for optimizing the design of a chip or system by decreasing the cost function that encompasses a plurality of constraints in the presence of variations in the design parameters is described. The method makes use of numerical optimization, simulated annealing, or any other objective-driven optimization means, and accounts for uncertainties in the modeling of the design variables and functions. A significant reduction in the number of design constraints which are violated at the end of an optimization process is achieved, even when all the design constraints cannot be satisfied. The optimization also reduces the cycle time at which the design operates and limits the increase in the minimum operational cycle time of a particular implementation in the presence of variations that cannot be modeled or unpredictable variations in delay introduced by elements of the design. The method for optimizing the design includes the steps of: defining an objective function computed from variables and functions of the design of the chip or system; deriving a merit function from the objective function by adding to it a plurality of separation terms; and minimizing the merit function which reduces the expected value of the objective function when confronted with significant variations of the design variables and functions.

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Philip Neil Strenski