International Business Machines Corporation

Philip M Ryan

Edward V Weber

Russell W Lavallee

Vincent F Sollitto, Jr

Hans C Pfeiffer

Frederick J Aichelmann, Jr

Donald E Davis

George L Bond

Richard D Moore

Frank P Cartman

Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.

Error logging memory system for avoiding miscorrection of triple errors

A hierarchical memory system is disclosed comprising at least one dual-ported memory level, each port having access to a separate bidirectional data bus. The port facing the higher memory levels is equipped with a pair of data buffers having a bit width equal to the bit width of a single row of cells in the storage array contained within the dual-ported level. One buffer (output) is loaded in one cycle from the array. The outer buffer (input) is emptied in one cycle into the array. Both buffers interact with the higher memory level independently of the transferring of data through the other of the dual ports. Thus, contention for the use of bus facilities and contention for memory cycles are greatly reduced in the transferring of data between the memory levels.

Hierarchical memories having two ports at each subordinate memory level

A fault alignment exclusion method and apparatus is disclosed which operates to prevent the alignment of two or more defective bit storage locations at an address in a memory array. The disclosed memory comprises a plurality (n.times.m) of separate memory chips arranged in a matrix of n rows and m columns. Each of the chips contains a large plurality (64K) of individually addressable bit locations. A plurality of data words, each containing m (72) bit positions are transferred from the memory array to a n (16) word m (72) bit position buffer during a memory read operation. Steering logic responsive to control signals is disposed between the memory and the buffer which permits the n chips in each column of the array to be effectively rearranged selectively within the respective columns so that the relationship of any given chip to a position of the 16 storage positions in a corresponding buffer column may be selectively changed by the control signals applied to the steering logic. The control signals are developed based on defect data stored in an error map such that each memory address contains no more than one defective location.

Multi-bit error scattering arrangement to provide fault tolerant

A method is disclosed for operating a fault tolerant memory system which is provided with a fault alignment exclusion mechanism of the type disclosed in copending application Ser. No. 388,834. The method allows the assignment of a new permute vector to the fault alignment mechanism even though the memory is operating and storing user data. The method rearranges the data in the affected column by transferring data in one chip to another chip in the column through a buffer under the control of the old and new permute vectors. The transfer operation involves transferring the data at the same bit position from each chip in the column to a buffer under the control of the old permute vector and then transferring the data from the buffer to the same bit positions in other chips in the column determined by the new permute vector. The memory is then returned to the user for normal operation.

Online realignment of memory faults

An online system is disclosed for mapping errors into an error map as data is transferred between a CPU and a relatively large fault tolerant semiconductor memory system without interfering with the normal use of the memory. The error mapping system permits a fault alignment exclusion mechanism to develop permute vectors which realign pair faults that were located at the same memory address. Having an up-to-date fault map which reflects the current error status of the memory when it is online and which reflects errors based on user data patterns greatly enhances the memory system and facilitates fault alignment exclusion efficiency.

System for updating error map of fault tolerant memory

A single error correcting memory is constructed from partially good components on the design assumption that the components are all-good. Those small number of logical lines containing double-bit errors are replaced when detected with good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement-page register. With such a memory architecture until the first double-bit error is detected (either in testing or actual use) all pages may be used for normal data storage. When such an error is detected some temporarily unused page in the memory is deal-located, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply by providing a different address in the replacement page register.

Dynamic replacement of defective memory words

Apparatus for high speed fault mapping of large memories

A method is disclosed for insuring that two semiconductor chips which have a 1-bit defect at the same chip address are not paired at any memory address by a fault alignment exclusion mechanism (FAEM) which functions to position chips having defects at different memory addresses. The FAEM employs an error map to determine which chips must be realigned in their respective columns and an address permute vector functions to effectively change the physical address of the chip in the column to a logical address. The two permute vectors for the two columns contributing to any uncorrectable error are 'exclusive-ORed' and the result stored in a second map along with an identification of the chip columns. Any time in the future that a new permute vector is proposed for assignment to any column of chips, the changed permute vector is exclusive-ORed with the permute vectors currently assigned to all other columns of the memory to see if any such combination produces a result forbidden by the forbidden result table. If no such forbidden result is found, the proposed permute vector can be assigned with the assurance that no pair of chips previously found to produce aligned faults will align now in any row of the memory. If any forbidden result is found, the proposed permute vector is discarded and a new one proposed.

Fault alignment exclusion method to prevent realignment of previously

This describes an automatic defect inspection system as could be applied to metallized masks or other patterns. The system causes each subfield to be individually aligned for inspection irrespective of the previous alignment of the pattern or any other sub-field. This is accomplished by scanning a preselected portion of each sub-field and adjusting the position of the scan based on the resulting signal while scanning a pre-established portion of the sub-field. In this way a portion of each sub-field is used as an alignment mark and stepping errors avoided. Once alignment is achieved a probe, comparable to the size of the minimum defect to be detected is scanned over the sub-field with an overlapping pattern to find defects such as excessive metal, metal in improper places or points where the metal is missing.

Pattern inspection tool - method and apparatus

In electron beam apparatus having a souce of electrons and a target area toward which the electrons are directed, electron beam forming means are provided along the path from the source to the target. These forming means include a first beam shaping member having a first spot shaping aperture therein, a second beam shaping member having a second spot shaping aperture therein, and means focusing the image of the first aperture in the plane of the second aperture to thereby form a composite spot shape defined by the image of the first aperture and the second aperture. Further means are provided for focusing the image of the composite spot in the target area. Preferably, the apertures are square shaped. Thus, by varying the position of the superimposed image of the first aperture with respect to the second aperture, a wide variety of rectangular shaped composite spots with different dimensions is obtainable. This permits the exposure of rectilinear patterns, e.g., in photoresists of integrated circuit fabrication, by the electron beam with a minimum of exposure steps and substantially no exposure overlap. The result is greatly increased speed in the total exposure of such rectilinear areas to the electron beam as well as a minimum of the 'blooming effects' produced by exposure overlap.

Method and apparatus for forming a variable size electron beam

A square-shaped electron beam is stepped from one predetermined position to another in a line-by-line scan to form a desired pattern on each chip of a semiconductor wafer to which the beam is applied. At each of the predetermined positions, the beam is on, off, or on for a portion of the time period at which the beam is disposed at the predetermined position. The beam also can be offset both along its direction of movement and perpendicular thereto at each of the predetermined positions. Control of this movement of the beam is obtained through utilizing a memory with no change being made in the memory if the predetermined position at the next line does not have any change from the predetermined position at the line along which the beam is moving.

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Hopewell Junction, NY, United States of America

Philip M Ryan